Intel VC820 Design Guide - Page 78
Additional Host Bus Guidelines, TCK/TMS Implementation Example for DP Designs
View all Intel VC820 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 78 highlights
Layout/Routing Guidelines Figure 2-41. TCK/TMS Implementation Example for DP Designs ITP Port RI TCK or TMS 1 KΩ Vcc2.5 non-inverting buffer 100 nH non-inverting buffer 100 nH SC242 Connector A motherboard trace 56 pF SC242 Connector B motherboard trace 56 pF itp vsd Table 2-14. Bus Request Connection Scheme for DP Intel® 820 Chipset Designs Bus Signal BREQ0# BREQ1# Agent 0 Pins BR0# BR1# Agent 1 Pins BR1# BR0# 2.12 Additional Host Bus Guidelines BREQ Pins UP Systems: For uni-processor systems, the BREQ0 pin should be pulled down to ground through a 10 Ω resistor. The BREQ1 pin should be left as a no-connect. Figure 2-42. Single Processor BREQ Strapping Requirements CPU #1 BREQ0# BREQ1# No Connect 2-52 Intel®820 Chipset Design Guide
Layout/Routing Guidelines
2-52
Intel
®
820 Chipset
Design Guide
2.12
Additional Host Bus Guidelines
BREQ Pins
UP Systems:
For uni-processor systems, the BREQ0 pin should be pulled down to ground through
a 10
Ω
resistor. The BREQ1 pin should be left as a no-connect.
Figure 2-41. TCK/TMS Implementation Example for DP Designs
Table 2-14. Bus Request Connection Scheme for DP Intel
®
820 Chipset Designs
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
TCK
or
TMS
ITP Port
Vcc2.5
1 K
Ω
R
I
100 nH
100 nH
56 pF
56 pF
SC242
Connector A
SC242
Connector B
itp vsd
non-inverting buffer
non-inverting buffer
motherboard trace
motherboard trace
Figure 2-42. Single Processor BREQ Strapping Requirements
CPU #1
BREQ0#
BREQ1#
No Connect