Intel VC820 Design Guide - Page 146
PCB Materials, 5.3.3 Design Process, Trace Geometry
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System Manufacturing 5.3.2 PCB Materials PCB tolerances determine Z0 variation. Those tolerances include trace width, pre-preg thickness, plating thickness, and dielectric constant. Pre-preg type impacts H tolerance and εr including single ply, 2-ply, and resin content. To design to the correct Z0 variation, PCB's typically need to meet the following (see Table 5-2): • Height tolerance ±10% (~ 0.4 mil) • Width tolerance ±2.5% (~ 0.4 mil) • εr tolerance ±5% (~0.2) Stackup Requirement: 28Ω ±10% Figure 5-1. 28Ω Trace Geometry W S T ε H 5.3.3 Design Process To meet the tight tolerances required a good design process to use is: • Specify the material to be used • Calculate board geometries for the desired impedance - or use the example stackup provided • Build test boards and coupons • Measure board impedance using a TDR and follow Intel's Impedance Test Methodology Document (found on developer.intel.com) • Measure geometries with cross-section • Adjust design parameters and/or material as required • Build a new board, re-measure the key parameters and be prepared to generate one or two board iterations This process will require iteration: design, build, test, modify, build, test... 5-2 Intel®820 Chipset Design Guide