Intel VC820 Design Guide - Page 115
Flight Time Hardware Validation, 3.3 Theory, 3.3.1 AGTL+
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Advanced System Bus Design double counting. TREF is defined as the time that it takes for the driver output pin to reach the measurement voltage, VREF, starting from the beginning of the driver transition at the pad. TREF must be generated using the same test load for TCO. Intel provides this timing value in the AGTL+ I/O buffer models. In this manner, the following valid delay equation is satisfied: Equation 3-5. Valid Delay Equation Valid Delay = TCO + TFLIGHT-SYS - TREF = TCO-MEASURED + TFLIGHT-MEASURED This valid delay equation is the total time from when the driver sees a valid clock pulse to the time when the receiver sees a valid data input. 3.2.6.3 Flight Time Hardware Validation When a measurement is made on the actual system, TCO and flight time do not need TREF correction since these are the actual numbers. These measurements include all of the effects pertaining to the driver-system interface and the same is true for the TCO. Therefore the addition of the measured TCO and the measured flight time must be equal to the valid delay calculated above. 3.3 Theory 3.3.1 AGTL+ AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave switching, open-drain bus with external pull-up resistors that provide both the high logic level and termination at each load. The processor AGTL+ drivers contain a full-cycle active pull-up device to improve system timings. The AGTL+ specification defines: • Termination voltage (VTT). • Receiver reference voltage (VREF) as a function of termination voltage (VTT). • processor termination resistance (RTT). • Input low voltage (VIL). • Input high voltage (VIH). • NMOS on resistance (RONN). • PMOS on resistance (RONP). • Edge rate specifications. • Ringback specifications. • Overshoot/Undershoot specifications. • Settling Limit. Intel®820 Chipset Design Guide 3-15