Intel VC820 Design Guide - Page 65
VREF Generation for AGP 2.0 (2X and 4X),
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Layout/Routing Guidelines Figure 2-31. AGP VDDQ Generation Example Circuit +12V O +3.3V O C2 47 uF VDDQ O R1 1 KΩ C1 1 uF TYPEDET# U1 LT1575 1 SHDN 2 VIN 3 GND 4 FB 5 IPOS 6 INEG GATE 7 8 COMP C4 10 pF C5 47 uF R5 7.5 KΩ 5 Ω C3 R2 220 uF R3 301 Ω R4 1.21 KΩ agp vddq generation vsd 2.7.8 VREF Generation for AGP 2.0 (2X and 4X) VREF generation for AGP 2.0 will be different depending on the AGP card type used. The 3.3V AGP cards generate VREF locally (i.e., they have a resistor divider on the card that divides VDDQ down to VREF) as shown in Figure 2-32. To account for potential differences between VDDQ and GND at the MCH and graphics controller, 1.5V cards use source generated VREF (i.e., the VREF signal is generated at the graphics controller and sent to the MCH, and another VREF is generated at the MCH and sent to the graphics controller). Refer to Figure 2-32. Both the graphics controller and the MCH are required to generate VREF and distribute it through the connector (1.5V add-in cards only). There are two pins defined on the AGP 2.0 universal connector to allow this VREF passing. These pins are: • VREFGC - Vref from the graphics controller to the chipset • VREFCG - Vref from the chipset to the graphics controller To preserve the common mode relationship between the VREF and data signals, it is important the routing of the two Vref signals must be matched in length to the strobe lines within 0.5 inches on the motherboard and within 0.25 inches on the add-in card. The voltage divider networks consists of AC and DC elements as shown in the figure. The VREF divider network should be placed as close to the AGP interface as is practical to get the benefit of the common mode power supply effects. However, the trace spacing around the VREF signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity. Intel®820 Chipset Design Guide 2-39