Intel VC820 Design Guide - Page 190
Game Port
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8 7 Game Port D J1BUTTON1 12 J2BUTTON1 12 JOY1X C 12 JOY2X 12 12 MIDI_OUT 12 JOY2Y JOY1Y 12 J2BUTTON2 12 J1BUTTON2 12 MIDI_IN 12 B A 8 7 6 5 4 3 2 1 R39 4.7K R35 4.7K R37 1K R36 1K R32 1K R33 1K VCC5 VCC5 VCC5 R38 47 C69 0.01UF 25V 10% C68 0.01UF 25V 10% C67 0.01UF 25V 10% C66 0.01UF 25V 10% VCC5 VCC5 VCC5 R24 2.2K 5% R23 2.2K R34 47 5% R22 2.2K 5% R21 2.2K 5% D VCC5 J5 DB15_AUD_STK 31 1 9 2 10 JOY1X_R 3 JOY2X_R 11 C 4 MIDI_OUT_R 12 5 JOY2Y_R 13 JOY1Y_R 6 14 7 MIDI_IN_R 15 8 32 1 1 + + + + C56 1 C54 C52 1 B 470PF C55 2 47PF C53 2 47PF C51 2 47PF 50V 50V 470PF 50V 2 47PF 50V Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point. A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: GAME PORT 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 27 OF 36 6 5 4 3 2 1