Intel VC820 Design Guide - Page 129

Clocking Clocking 4 4.1 Clock Generation There are two clock generator components required in an Intel® 820 chipset based system. The Direct Rambus* Clock Generator (DRCG) generates clock for the Direct Rambus* interface while the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the Intel CK98 Clock Specification are suitable for an Intel® 820 chipset based system. The CK133 generates the clocks listed in Table 4-1. Table 4-1. Intel® 820 Chipset Platform System Clocks Number Name on CK133 Used for Routed to Name on Receiver Frequency Voltage 2 Processors CLK 4 CPUCLK[0-3] System Bus Clock MCH HCLKIN 100/133 MHz 2.5V ITP BCLK 3 APIC[0-2] APIC Bus Clock 2 Processors PICCLK 33 MHz ICH APICCLK 2.5V PCI Bus Clock 5 PCI Devices CLK 8 PCI, LPC, FWH Flash PCICLK[1-7,F] BIOS Bus Clock ICH PCICLK 33 MHz FWH Flash BIOS Interface Clock FWH Flash BIOS CLK 3.3V LPC Interface Clock LPC CLK Hub Interface/AGP Bus Clock MCH CLK66 4 3V66[0-3] Hub Interface Clock AGP Bus Clock Unused ICH AGP device/ slot N/A CLK66 CLK N/A 66 MHz 3.3V 2 REF[0-1] Internal ICH Logic ICH Internal Super I/O Logic Super I/O CLK14 Vendor Specific 14 MHz 3.3V 1 48 MHz USB ICH DRCG Reference Clock DRCG 2 CPU_DIV2[0-1] Unused N/A CLK48 REFCLK N/A 48 MHz 50/66 MHz 3.3V 2.5V The CK133 is a mixed voltage component. Some of the output clocks are 3.3V and some of the output clock are 2.5V. As a result, the CK133 device requires both 3.3V and 2.5V. These power supplies should be a clean as possible. Noise in the power delivery system for the clock driver can cause noise on the clock lines. The MCH uses the same clock for hub interface and AGP. It is important that the hub interface/AGP clocks are routed to ensure the skew requirements are met between: • The MCH hub interface/AGP clock and the AGP connector (or device) Intel®820 Chipset Design Guide 4-1