Intel VC820 Design Guide - Page 66
AGP 2.0 VREF Generation & Distribution, must be 0.4VDDQ. However, during 1.5V AGP 2.0
View all Intel VC820 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 66 highlights
Layout/Routing Guidelines During 3.3V AGP 2.0 operation, VREF must be 0.4VDDQ. However, during 1.5V AGP 2.0 operation, Vref must be 0.5VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, and one such example is shown in Figure 2-32. Figure 2-32. AGP 2.0 VREF Generation & Distribution 1.5V AGP Card +12V O R7 1K Note: R7 is the same resistor seen in AGP VDDQ Generation Example Circuit Figure (R1) TYPEDET# VrefGC R9 300 1% R11 200 1% VDDQ 500pF C8 VDDQ AGP REF Device GND U6 mosfet VDDQ REF MCH 0.1uF C10 GND Place C10 close to the MCH R6 R5 1K 82 R2 R4 1K 82 500pF C9 3.3V AGP Card VrefCG The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG signals must be 5 mils wide and routed 25 mils from adjacent signals. +12V O Note: R7 is the same resistor seen in AGP VDDQ Generation Example Circuit Figure R7 (R1) 1K TYPEDET# VrefGC R9 300 1% VDDQ R11 200 1% 500pF C8 VDDQ AGP REF Device GND VrefCG U6 mosfet 0.1uF C10 VDDQ REF MCH GND Place C10 close to the MCH R6 R5 1K 82 R2 R4 1K 82 500pF C9 The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG signals must be 5 mils wide and routed 25 mils from adjacent signals. The flexible VREF divider shown in Figure 2-32 uses a FET switch to switch between the locally generated VREF (for 3.3V add-in cards) and the source generated VREF (for 1.5V add-in cards). Usage of the source generated VREF at the receiver is optional and is a product implementation issue which is beyond the scope of this document. 2-40 Intel®820 Chipset Design Guide