Intel VC820 Design Guide - Page 226

8 7 PCI Connectors 2 and 3 VCC3_3 VCC12- VCC5 PCI Slot 2 J10 PCI3_CON B1 A1 PTCK B2 A2 D 22,23 B3 A3 B4 A4 B5 A5 B6 A6 10,18,21,22,23,34 10,22,23,34 23 PIRQ#A PIRQ#C PRSNT#31 B7 A7 B8 A8 B9 A9 B10 A10 PRSNT#32 23 B11 A11 B12 A12 B13 A13 B14 A14 B15 A15 PCLK3 7 B16 A16 B17 A17 10,34 PREQ#2 B18 A18 B19 A19 AD31 B20 A20 C AD29 B21 A21 B22 A22 AD27 B23 A23 AD25 B24 A24 B25 A25 C_BE#3 B26 A26 AD23 B27 A27 B28 A28 AD21 B29 A29 AD19 B30 A30 B31 A31 AD17 B32 A32 C_BE#2 B33 A33 B34 A34 10,18,22,23,34 IRDY# B35 A35 B36 A36 10,18,22,23,34 DEVSEL# B37 A37 B38 A38 PLOCK# B39 A39 10,22,23,34 PERR# B40 A40 B 10,18,22,23,34 B41 A41 10,18,22,23,34 SERR# B42 A42 B43 A43 C_BE#1 B44 A44 AD14 B45 A45 B46 A46 AD12 B47 A47 AD10 B48 A48 B49 A49 AD8 B52 A52 AD7 B53 A53 B54 A54 AD5 B55 A55 AD3 B56 A56 B57 A57 A AD1 B58 A58 B59 A59 PU3_ACK64# 23 B60 A60 B61 A61 B62 A62 10,18,22 C_BE#[3:0] 10,18,22 AD[31:0] 8 7 key key 6 5 4 3 2 1 VCC3_3 VCC3_3 VCC3_3 VCC5 VCC12 VCC12- VCC5 PCI Slot 3 J9 PCI3_CON VCC5 VCC12 J9 must be furthest from the processor. PTRST# 22,23 PTMS PTDI 22,23 22,23 22,23 PTCK B1 A1 B2 A2 B3 A3 B4 A4 B5 A5 PTRST# PTMS PTDI 22,23 22,23 22,23 D VCC5 PIRQ#D B6 A6 PIRQ#C PIRQ#B 10,22,23,34 PIRQ#D B7 A7 PIRQ#A 10,22,23,34 RP13 10,22,23,34 10,18,21,22,23,34 SDONEP3 1 8 10,21,22,23,34 PIRQ#B B8 A8 23 10,21,22,23,34 SDONEP4 2 7 PRSNT#41 B9 A9 23 23 VCC3_3SBY SBOP3 3 6 PCI_TEST for debug only11 PCI_TEST B10 A10 GNT#A for debug only 23 VCC3_3SBY PRSNT#42 B11 A11 GNT#A_R R99 GNT#A 10,34 SBOP4 4 5 23 23 B12 A12 0K 5.6K SERIRQ for debug only B13 A13 R107 10,14,34 SERIRQ R255 SERIRQ_RB14 A14 VAUX_JP 0K PCIRST# PGNT#2 PCI_PME# AD30 8,10,12,13,14,18,21,22,23,24 7 10,34 10,34 10,18,21,22,23 AD31 0K PCLK4 PREQ#5 B15 A15 B16 A16 B17 A17 B18 A18 B19 A19 B20 A20 PCIRST# R110 REQ#A 10,34 8,10,12,13,14,18,21,22,23,24 0K No Stuff R110. PGNT#5 10,34 REQ#A for debug only PCI_PME# AD30 10,18,21,22,23 C112 0.1UF PRSNT#31 23 C121 0.1UF PRSNT#32 23 AD28 AD29 B21 A21 B22 A22 AD28 C116 0.1UF PRSNT#41 23 C AD26 AD24 AD27 AD25 B23 A23 B24 A24 B25 A25 AD26 AD24 C126 0.1UF PRSNT#42 23 C_BE#3 AD23 B26 A26 B27 A27 R_AD22 23 AD22 B28 A28 AD22 AD20 AD21 B29 A29 AD20 AD19 B30 A30 AD18 B31 A31 AD18 AD16 AD17 B32 A32 AD16 C_BE#2 B33 A33 FRAME# 10,18,22,23,34 IRDY# B34 A34 B35 A35 FRAME# VCC5 TRDY# 10,18,22,23,34 STOP# 10,18,22,23,34 SDONEP3 23 SBOP3 23 PAR 10,18,22,23 AD15 DEVSEL# PLOCK# PERR# SERR# C_BE#1 B36 A36 B37 A37 B38 A38 B39 A39 B40 A40 B41 A41 B42 A42 B43 A43 B44 A44 TRDY# STOP# SDONEP4 23 SBOP4 23 PAR AD15 PU3_ACK64# R174 23 2.7K PU3_REQ64# R175 23 2.7K PU4_ACK64# R172 B 23 2.7K PU4_REQ64# 23 R173 2.7K AD14 B45 A45 AD13 B46 A46 AD13 AD11 AD12 B47 A47 AD11 AD10 B48 A48 AD9 B49 A49 AD9 AD23 10,18,22,23 R118 100 R_AD23 C_BE#0 AD6 AD8 B52 A52 C_BE#0 AD7 B53 A53 B54 A54 AD6 AD22 10,18,22,23 R117 100 R_AD22 23 AD4 AD5 B55 A55 AD4 AD3 B56 A56 AD2 B57 A57 AD2 AD0 AD1 B58 A58 AD0 B59 A59 A PU3_REQ64# 23 PU4_ACK64# 23 B60 A60 B61 A61 PU4_REQ64# 23 B62 A62 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 3 AND 4 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 23 OF 38 6 5 4 3 2 1