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Table 2-5. Line Matching and Via Compensation Example

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Layout/Routing Guidelines Table 2-5. Line Matching and Via Compensation Example1,2,3,4,5,6,7,8,9,10 Signal Ball on MCH Nominal RSL Length (mils) Package Dimension (mils) Motherboard Trace Length when Routed on Bottom (i.e., Real Via) Min (mils) Max (mils) Motherboard Trace Length when Routed on Top (i.e., Dummy Via) Min (mils) Max (mils) Recommended To Route On DQA0 A13 DQA1 C13 DQA2 A14 DQA3 C14 DQA4 B14 DQA5 C15 DQA6 A15 DQA7 C16 DQA8 A16 DQB0 C7 DQB1 B7 DQB2 C6 DQB3 A6 DQB4 C5 DQB5 A5 DQB6 B5 DQB7 A4 DQB8 C4 RQ0 A7 RQ1 C8 RQ2 A8 RQ3 C9 RQ4 B9 RQ5 A9 RQ6 A10 RQ7 C10 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 CFM A12 CFM# B12 CTM B11 CTM# A11 2000 2000 2000 2000 138.14 19.11 163.16 39.87 97.54 62.67 186.11 95.70 230.20 39.56 95.83 63.49 153.69 97.33 191.43 152.47 237.71 138.29 179.49 27.12 162.21 5.80 71.70 133.88 122.20 0.00 132.37 64.63 56.06 126.34 Formula A 1851.86 1970.89 1826.84 1950.13 1892.46 1927.33 1803.90 1894.30 1759.81 1950.44 1894.17 1926.51 1836.31 1892.67 1798.57 1837.53 1752.29 1851.71 1810.51 1962.88 1827.79 1984.20 1918.30 1856.12 1867.81 1990.00 1871.86 1990.89 1846.84 1970.13 1912.46 1947.33 1823.90 1914.30 1779.81 1970.44 1914.17 1946.51 1856.31 1912.67 1818.57 1857.53 1772.29 1871.71 1830.51 1982.88 1847.79 2004.20 1938.30 1876.12 1887.81 2010.00 FORMULA C 1906.85 1976.02 1984.76 1913.01 Formula B 1876.86 1995.89 1851.84 1975.13 1917.46 1952.33 1828.90 1919.30 1784.81 1975.44 1919.17 1951.51 1861.31 1917.67 1823.57 1862.53 1777.29 1876.71 1835.51 1987.88 1852.79 2009.20 1943.30 1881.12 1892.81 2015.00 1896.86 2015.89 1871.84 1995.13 1937.46 1972.33 1848.90 1939.30 1804.81 1995.44 1939.17 1971.51 1881.31 1937.67 1843.57 1882.53 1797.29 1896.71 1855.51 2007.88 1872.79 2029.20 1963.30 1901.12 1912.81 2035.00 FORMULA D 1932.37 2001.54 2010.29 1938.53 Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom Bottom Bottom Top Top NOTES: 1. Signals connecting to the "A" side of the RIMM connector (i.e., A1, A2, A3, etc.) should be routed on the top (primary side) of the motherboard; 2. Signals connecting to the "B" side of the RIMM connector should be routed on bottom (solder side). 3. These trace lengths ONLY apply from MCH to the 1st RIMM. All signals must match EXACTLY from RIMM to RIMM. 4. Clock trace lengths include 1.021 trace velocity factor. 5. Formula A min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil 6. Formula A max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil 7. Formula B min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil + 25 mil 8. Formula B max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil + 25 mil 9. Formula C: Motherboard Trace = (Nominal RSL Length - Package Dimension) * 1.021 10.Formula D: Motherboard Trace = (Nominal RSL Length - Package Dimension + 25 mil) * 1.021 2-24 Intel®820 Chipset Design Guide

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

Layout/Routing Guidelines

2-24

Intel

820 Chipset

Design Guide

NOTES:

1. Signals connecting to the

"A"

side of the RIMM connector (i.e., A1, A2, A3, etc.) should be routed on the top

(primary side) of the motherboard;

2. Signals connecting to the "B" side of the RIMM connector should be routed on bottom (solder side).

3. These trace lengths ONLY apply from MCH to the 1st RIMM. All signals must match EXACTLY from RIMM to

RIMM.

4. Clock trace lengths include 1.021 trace velocity factor.

5. Formula

min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil

6. Formula

max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil

7. Formula

min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil + 25 mil

8. Formula

max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil + 25 mil

9. Formula

: Motherboard Trace = (Nominal RSL Length - Package Dimension) * 1.021

10.Formula

: Motherboard Trace = (Nominal RSL Length - Package Dimension + 25 mil) * 1.021

Table 2-5. Line Matching and Via Compensation Example

1,2,3,4,5,6,7,8,9,10

Signal

Ball

MCH

Nominal

RSL

Length

(mils)

Package

Dimension

(mils)

Motherboard Trace

Length when

Routed on Bottom

(i.e., Real Via)

Motherboard Trace

Length when

Routed on Top

(i.e., Dummy Via)

Recommended

To Route On

Min

(mils)

Max

(mils)

Min

(mils)

Max

(mils)

Formula A

Formula B

DQA0

A13

2000

138.14

1851.86

1871.86

1876.86

1896.86

Top

DQA1

C13

2000

19.11

1970.89

1990.89

1995.89

2015.89

Bottom

DQA2

A14

2000

163.16

1826.84

1846.84

1851.84

1871.84

Top

DQA3

C14

2000

39.87

1950.13

1970.13

1975.13

1995.13

Bottom

DQA4

B14

2000

97.54

1892.46

1912.46

1917.46

1937.46

Top

DQA5

C15

2000

62.67

1927.33

1947.33

1952.33

1972.33

Bottom

DQA6

A15

2000

186.11

1803.90

1823.90

1828.90

1848.90

Top

DQA7

C16

2000

95.70

1894.30

1914.30

1919.30

1939.30

Bottom

DQA8

A16

2000

230.20

1759.81

1779.81

1784.81

1804.81

Top

DQB0

2000

39.56

1950.44

1970.44

1975.44

1995.44

Bottom

DQB1

2000

95.83

1894.17

1914.17

1919.17

1939.17

Top

DQB2

2000

63.49

1926.51

1946.51

1951.51

1971.51

Bottom

DQB3

2000

153.69

1836.31

1856.31

1861.31

1881.31

Top

DQB4

2000

97.33

1892.67

1912.67

1917.67

1937.67

Bottom

DQB5

2000

191.43

1798.57

1818.57

1823.57

1843.57

Top

DQB6

2000

152.47

1837.53

1857.53

1862.53

1882.53

Bottom

DQB7

2000

237.71

1752.29

1772.29

1777.29

1797.29

Top

DQB8

2000

138.29

1851.71

1871.71

1876.71

1896.71

Bottom

RQ0

2000

179.49

1810.51

1830.51

1835.51

1855.51

Top

RQ1

2000

27.12

1962.88

1982.88

1987.88

2007.88

Bottom

RQ2

2000

162.21

1827.79

1847.79

1852.79

1872.79

Top

RQ3

2000

5.80

1984.20

2004.20

2009.20

2029.20

Bottom

RQ4

2000

71.70

1918.30

1938.30

1943.30

1963.30

Top

RQ5

2000

133.88

1856.12

1876.12

1881.12

1901.12

Bottom

RQ6

A10

2000

122.20

1867.81

1887.81

1892.81

1912.81

Top

RQ7

C10

2000

0.00

1990.00

2010.00

2015.00

2035.00

Bottom

FORMULA C

FORMULA D

CFM

A12

2000

132.37

1906.85

1932.37

Bottom

CFM#

B12

2000

64.63

1976.02

2001.54

Bottom

CTM

B11

2000

56.06

1984.76

2010.29

Top

CTM#

A11

2000

126.34

1913.01

1938.53

Top