Intel VC820 Design Guide - Page 76
Table 2-13. Processor and 82820 MCH Connection Checklist, Continued, CMOS Signals, TAP Signals
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Layout/Routing Guidelines Table 2-13. Processor and 82820 MCH Connection Checklist1,2 (Continued) CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1) CMOS Signals A20M# FERR# FLUSH# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI PICD[1:0] PREQ# PWRGOOD SLP# SMI# STPCLK# THERMTRIP# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor 150 Ω pull up to Vcc2.5 (not used by chipset). Connect to 2nd processor 150 Ω pull up to Vcc2.5 if tied to custom logic or leave as N/C (not used by chipset). 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor Connect to 2nd processor 150 Ω pull up to Vcc2.5, connect to ICH and FWH Flash BIOS 150 Ω pull up to Vcc2.5, connect to ICH 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor Connect to 2nd processor Connect to 2nd processor 150 Ω pull up to Vcc2.5, connect to ICH Two 300-330 Ω pull ups to Vcc2.5 located at each end of trace. Connect to 2nd processor ~200-330 Ω pull up to Vcc2.5, connect to ITP ~200-330 Ω pull up to Vcc2.5, connect to pin 16 ITP pin 20 150-330 Ω pull up to 2.5V, output from the PWRGOOD logic Connect to 2nd processor 150 Ω pull up to Vcc2.5, connect to ICH 150 Ω pull up to Vcc2.5, connect to ICH 150 Ω pull up to Vcc2.5, connect to ICH 150 Ω pull up to Vcc2.5 and connect to power off logic or ASIC, or leave as N/C Connect to 2nd processor. Could tie separately to a monitoring ASIC. TAP Signals PRDY# TCK TDO TDI TMS TRST# 150 Ω pull up to VTT, 240 Ω series resistor to 150 Ω pull up to VTT, 240 Ω series resistor ITP pin 18 to ITP pin 22 1k Ω pull up to Vcc2.5, 47 Ω series resistor to ITP pin 5 Each processor should receive a separately buffered copy of TCK from the ITP. Tank circuit is optional for signal integrity. See 150 Ω pull up to Vcc2.5 and connect to ITP 10 TDO of CPU1 is connected to the ITP TDO pin 10. Pull up both sets of TDI/TDO nets as described. ~150-330 Ω pull up to Vcc2.5 and connect to ITP pin 8 TDI of CPU0 is connected to the ITP pin 8, TDI of CPU1 is connected to TDO of CPU0. Pull up both sets of TDI/TDO nets as described. 1 KΩ pull up to Vcc2.5, 47 Ω series resistor to ITP pin 7 ~680 Ω pull down, connect to ITP pin 12 Each processor should receive a separately buffered copy of TMS from the ITP. Tank circuit is optional for signal integrity. See Connect to 2nd processor 2-50 Intel®820 Chipset Design Guide