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Intel VC820 Design Guide - Page 236

ATX Connector, Reset Button, SN74LVC06A has 5V input tolerance.

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8 7 6 5 4 3 2 1 Power Connector ITP Reset circuit. For debug only. D 74LVC14A has 5V input tolerance. D VCC3_3SBY VCC3_3SBY VCC3_3SBY VCC5SBY VCC3_3SBY VCC12VCC5M VCC3_3 ATX Connector VCC5SBY VCC12 J24 U15 14 1 74LVC14A7 U15 14 2 POK_U1 3 74LVC14A7 4 POK_U2 1 14 2 U3 3 POK_U3 SN74LVC087A 4.7K R347 U20 14VCC 11,31 SLP_S3# 5 6 SN74LVC06A7 GND VCC5 SLP_S3 C SN74LVC06A has 5V output tolerance. 11 3_3V11 3_3V1 1 12 -12V 3_3V2 2 13 GND13 GND3 3 14 PS_0N ATX 5V4 4 15 GND15 GND5 5 16 GND16 5V6 6 17 GND17 GND7 7 18 -5V PW_OK 8 19 5V19 5VSB 9 20 5V20 12V 10 DBRESET# 4 330 ohm pullup to VCC3_3 located on CPU sheet. R339 0K VCC3_3SBY SN74LVC06A has 5V input tolerance. VCC5SBY U20 14VCC 1 2 SN74LVC06A7 GND 220 ohm pullup to VCC3_3 is located on VRM sheet. VCC3_3SBY VCC3_3SBY U23 14 SLOTOCC0# 5 30 VRM_PWRGD 1 14 6 2 U9 3 4 74LVC14A7 7 SN74LVC08A B VCC5SBY VCC3_3SBY VCC3_3SBY U22 1 14 3 2 7 74LVC32 ATX_PWOK R342 ATX_PWOK_R 0K No stuff R342 when ITP is used. VCC3_3SBY 9 14 U9 8 10 SN74LVC087A VCC3_3SBY U18 74LS1932 14VCC 8 10 7 GND PWROK_INV VCC3_3SBY VCC3_3SBY U20 14VCC 3 4 SN74LVC06A7 GND VCC3_3SBY R348 R349 R96 1M 4.7K 330 VCC2_5 C PWRGOOD 4,6 VCC3_3SBY PWROK 9,11,18,31 B No stuff. For test only SLOTOCC1# U23 14 9 30 VRM1_PWRGD 1 14 8 2 U26 3 6 74LVC14A7 7 SN74LVC08A Reset Button A SW2 JP12 RSTBTN_SW R343 22 VCC3_3SBY R372 220K VCC3_3SBY VCC3_3SBY C335 0.01UF U23 14 3 4 74LVC14A7 C328 10UF U23 14 RS_SCH 1 2 74LVC14A7 8 7 6 5 R251 22K RSMRST_U U15 14 5 6 74LVC14A7 C266 1UF U15 14 RSMRST 9 8 74LVC14A7 R288 1M RSMRST# 11,19 No stuff. For test only A Resume Reset circuitry using a 22 msec delay and Schmitt trigger logic. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: POWER CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 33 OF 38 4 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:46

POWER CONNECTOR

RSTBTN_SW

JP12

U26

SN74LVC08A

SLOTOCC1#

30 VRM1_PWRGD

U23

RS_SCH

U20

9,11,18,31

PWROK

R339

R342

R288

R251

22K

11,31

SLP_S3#

R347

4.7K

SLP_S3

R343

PWRGOOD

4,6

330

R96

R348

ATX_PWOK

POK_U1

POK_U2

POK_U3

RSMRST#

11,19

RSMRST

RSMRST_U

ATX_PWOK_R

PWROK_INV

U15

U20

U15

U20

DBRESET#

10UF

C328

C335

0.01UF

1UF

C266

U15

J24

SW2

VRM_PWRGD

U18

R349

4.7K

SN74LVC08A

SLOTOCC0#

220K

R372

U22

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VCC3_3SBY

74LVC14A

VCC3_3SBY

74LVC14A

VCC3_3SBY

VCC5SBY

74LVC14A

VCC3_3SBY

SN74LVC06A

GND

VCC

VCC3_3SBY

VCC5M

VCC12-

VCC12

VCC5

VCC5SBY

VCC3_3

VCC5SBY

VCC2_5

VCC5SBY

VCC3_3SBY

74LVC14A

SN74LVC06A

GND

VCC

VCC3_3SBY

74LVC14A

VCC3_3SBY

SN74LVC06A

GND

VCC

74LVC14A

ATX

3_3V11

-12V

GND13

PS_0N

GND15

GND16

GND17

-5V

5V19

5V20

3_3V1

3_3V2

GND3

5V4

GND5

5V6

GND7

PW_OK

5VSB

12V

SN74LVC08A

74LS132

VCC

GND

SN74LVC08A

VCC3_3SBY

74LVC32

330 ohm pullup to VCC3_3 located on CPU sheet.

For test only

and Schmitt trigger logic.

using a 22 msec delay

Resume Reset circuitry

No stuff.

For test only

No stuff.

ATX Connector

74LVC14A has 5V input tolerance.

ITP Reset circuit.

For debug only.

SN74LVC06A has 5V input tolerance.

SN74LVC06A has 5V output tolerance.

No stuff R342 when ITP is used.

Power Connector

Reset Button

220 ohm pullup to VCC3_3 is located on VRM sheet.