Intel VC820 Design Guide - Page 217
Lpc47b27x, Serial Port 1, Fdc I/f, Infrared I/f, Clocks, Kybd/mse I/f, Parallel Port I/f
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8 Super I/O 7 VCC3_3 28 VCC5_KBMS_J D KBDAT 28 KBCLK 28 MDAT 28 MCLK 28 RP5 8 1 7 2 6 3 5 4 4.7K R315 11,12,14 11,12,14 4.7K 11,12,14 11,12,14 11,12,14 11,14 8,10,12,13,14,18,21,22,23,24 11 10,14,23,34 7,14 10,34 10,34 IRRX C 20 IRTX 20 27 C320 C317 27 27 470PF 470PF 27 27 27 27 27 27 27 27 27 27 27 LPC header. For debug only. 27 B J20 27 11,12,14 LAD3/FWH3 1 2 11,12,14 LAD2/FWH2 3 4 28 11,12,14 LAD1/FWH1 5 6 28 11,12,14 LAD0/FWH0 7 8 28 11,12,14 LFRAME#/FWH4 9 10 28 8,10,12,13,14,18,21,22,23,24PCIRST# 11 12 28 7,14 SIO_PCLK7 13 14 28 11,14 LDRQ#0 15 16 28 17 18 28 7,11 MULT1_GPIO 19 20 28 21 22 28 10,14,23,34 SERIRQ 23 24 28 25 26 28 27 28 28 28 A 7 8 7 6 5 4 3 2 1 VCC5 VCC3_3 VREF 44 VTR 18 VCC1 53 VCC2 65 VCC3 93 LFRAME#/FWH4 LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 LDRQ#0 PCIRST# LPCPD# LPC_PME# SERIRQ SIO_PCLK7 KBRST# A20GATE RXD0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0 RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 DRVDEN#1 DRVDEN#0 MTR#0 DS#0 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK#0 WRTPRT# RDATA# DSKCHG# SIO_14MHZ 6 U17 24 LFRAME# 23 LAD3 22 LAD2 21 LAD1 20 LAD0 25 LDRQ# 26 LRESET# 27 LPCPD# 17 PME# 30 SERIRQ 29 PCI_CLK 56 KDAT 57 KCLK 58 MDAT 59 MCLK 63 KBDRST 64 A20GATE 61 IRRX2/GP34 62 IRTX2/GP35 84 RXD1 85 TXD1 86 DSR1# 87 RTS1# 88 CTS1# 89 DTR1# 90 RI1# 91 DCD1# 95 RXD2_IRRX 96 TXD2_IRTX 97 DSR2# 98 RTS2# 99 CTS2# 100 DTR2# 92 RI2# 94 DCD2# 2 DRVDEN1 1 DRVDEN0 3 MTR0# 5 DS0# 8 DIR# 9 STEP# 10 WDATA# 11 WGATE# 12 HDSEL# 13 INDEX# 14 TRK0# 15 WRTPRT# 16 RDATA# 4 DSKCHG# 6 CLKI32 19 CLOCKI LPC I/F PARALLEL PORT I/F SIO LPC47B27X KYBD/MSE I/F INIT# 66 PAR_INIT# SLCTIN# 67 SLIN# PD7 75 PDR7 PD6 74 PDR6 PD5 73 PDR5 PD4 72 PDR4 PD3 71 PDR3 PD2 70 PDR2 PD1 69 PDR1 PD0 68 PDR0 SLCT# 77 SLCT PE 78 PE BUSY 79 BUSY ACK# 80 ACK# ERROR# 81 ERR# ALF# 82 AFD# STROBE# 83 STB# INFRARED I/F FAN2/GP32 54 FAN1/GP33 55 FDC_PP/DDRC/GP43 28 PWM2 PWM1 26 PDR[7:0] 26 26 26 26 26 26 26 26 26 20 20 SERIAL PORT 1 VCC5 VCC3_3 D 1 C349 C309 C348 C321 C313 C323 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 + 2.2UF Place next to VREF. Place decoupling caps near each power pin. C VCC3_3 VCC3_3 R157 4.7K R313 4.7K SERIAL PORT 2 GP60/LED1 48 GP61/LED2 49 GP27/IO_SMI# 50 GP30/FAN_TACH2 51 LPC_SMI# 11 CPU_TACH2 B GP31/FAN_TACH1 52 CPU_TACH1 GP25/MIDI_IN 46 GP26/MIDI_OUT 47 MIDI_IN 29 MIDI_OUT 29 FDC I/F GP10/J1B1 32 GP11/J1B2 33 GP12/J2B1 34 GP13/J2B2 35 GP14/J1X 36 GP15/J1Y 37 GP16/J2X 38 GP17/J2Y 39 GP20/P17 41 GP21/P16 42 GP22/P12 43 J1BUTTON1 29 J1BUTTON2 29 J2BUTTON1 29 J2BUTTON2 29 JOY1X 29 JOY1Y 29 JOY2X 29 JOY2Y 29 KEYLOCK# 20 CLOCKS GP24/SYSOPT 45 SYSOPT Pulldown on SYSOPT for IO address of 0x02E A 4.7K 7 GND1 31 GND2 60 GND3 76 GND4 40 AVSS R312 5 4 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SUPER I/O 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 14 OF 38 3 2 1