Intel VC820 Design Guide - Page 184

PCI CONNECTORS 3 AND 4

11-9-1999_11:43

21

J11

A2

A21

A27

A33

A39

A45

B25

B31

B36

B43

A53

B54

A5

A8

A10

A16

B5

B6

A59

A61

A62

B59

B61

B62

B19

B1

B60

A58

B58

B48

A47

B47

A46

B45

A44

A32

B32

A31

B30

A57

A29

B29

A28

B27

A25

B24

A23

B23

A22

B21

B56

A20

B20

A55

B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

A9

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B3

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

A6

B7

A7

B8

B35

B39

A43

B40

A19

B9

B11

B2

B4

A4

A3

A1

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A38

A36

B41

J12

B41

A36

A38

B42

A40

A41

A15

B14

B10

A14

A11

A60

B18

A1

A3

A4

B4

B2

B11

B9

A19

B40

A43

B39

B35

B8

A7

B7

A6

A26

A17

B28

B57

A56

B49

B46

B38

B34

B22

B17

B15

B13

B12

B3

A48

A42

A37

A35

A30

A24

A18

A13

A12

A34

B37

A9

B16

B26

B33

B44

A52

A49

B52

B53

A54

B55

A55

B20

A20

B56

B21

A22

B23

A23

B24

A25

B27

A28

B29

A29

A57

B30

A31

B32

A32

A44

B45

A46

B47

A47

B48

B58

A58

B60

B1

B19

B62

B61

B59

A62

A61

A59

B6

B5

A16

A10

A8

A5

B54

A53

B43

B36

B31

B25

A45

A39

A33

A27

A21

A2

VAUX_JP

R110

R107

SDONEP3

21

SDONEP4

21

SBOP3

21

SBOP4

21

PRSNT#31

21

PRSNT#32

21

PRSNT#41

21

PRSNT#42

21

PU3_ACK64#

21

PU3_REQ64#

21

PU4_ACK64#

21

PU4_REQ64#

21

AD23

8,16

AD22

8,16

R_AD23

21

R_AD22

21

5

PCLK4

21

R_AD22

PCIRST#

6,8,10,11,12,16,19,20,21,22

FRAME#

8,16,20,21,32

PTCK

20,21

PCLK3

5

IRDY#

8,16,20,21,32

DEVSEL#

8,16,20,21,32

PLOCK#

8,20,21,32

PERR#

8,16,20,21,32

SERR#

8,16,20,21,32

STOP#

8,16,20,21,32

TRDY#

8,16,20,21,32

PCI_PME#

8,16,19,20,21

C_BE#[3:0]

8,16,20

C_BE#3

C_BE#2

C_BE#1

C_BE#0

C_BE#0

C_BE#1

C_BE#2

C_BE#3

R118

100

R117

100

RP13

5.6K

8

7

6

5

4

3

2

1

R174

2.7K

R175

2.7K

R172

2.7K

R173

2.7K

PTMS

20,21

PTRST#

20,21

PTDI

20,21

PRSNT#31

21

PRSNT#32

21

PAR

8,16,20,21

SBOP3

21

SDONEP3

21

8,20,21,32

PIRQ#D

8,19,20,21,32

PIRQ#B

21

PRSNT#41

21

PRSNT#42

20,21

PTRST#

6,8,10,11,12,16,19,20,21,22

PCIRST#

8,16,19,20,21

PCI_PME#

IRDY#

DEVSEL#

PLOCK#

PERR#

SERR#

PAR

21

SBOP4

21

SDONEP4

STOP#

TRDY#

FRAME#

8,16,19,20,21,32

PIRQ#A

8,20,21,32

PIRQ#C

20,21

PTDI

20,21

PTMS

20,21

PTCK

PREQ#2

8,32

8,32

PGNT#2

PIRQ#B

8,19,20,21,32

PIRQ#D

8,20,21,32

PIRQ#A

8,16,19,20,21,32

PIRQ#C

8,20,21,32

8,32

PGNT#5

8,32

PREQ#5

8,12,32

SERIRQ

AD[31:0]

8,16,20

AD3

AD0

AD28

AD30

AD26

AD24

AD22

AD20

AD18

AD16

AD13

AD11

AD9

AD6

AD4

AD2

AD3

AD5

AD7

AD17

AD31

AD29

AD27

AD25

AD23

AD21

AD19

AD14

AD12

AD10

AD8

AD1

AD2

AD4

AD6

AD9

AD11

AD13

AD15

AD16

AD18

AD20

AD22

AD26

AD28

AD0

AD1

AD8

AD10

AD12

AD14

AD19

AD21

AD23

AD25

AD27

AD29

AD31

AD17

AD7

AD5

AD30

AD15

AD24

R255

8,32

GNT#A

8,32

REQ#A

R_AD23

21

GNT#A_R

SERIRQ_R

R99

21

PU3_ACK64#

21

PU3_REQ64#

21

PU4_ACK64#

21

PU4_REQ64#

C112

0.1UF

C121

0.1UF

C116

0.1UF

C126

0.1UF

9

PCI_TEST

PCI3_CON

key

PCI3_CON

key

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

2

1

A

B

C

D

1

2

3

4

5

6

7

8

D

C

B

A

1.0

TITLE: INTEL(R) 820 CHIPSET - FCPGA

REFERENCE BOARD

OF 37

R

0K

0K

VCC5

VCC5

VCC12

VCC3_3

VCC5

VCC5

VCC12-

VCC12-

VCC3_3

VCC5

VCC5

VCC3_3

VCC12

VCC3_3

VCC3_3SBY

0K

VCC3_3SBY

0K

PCI Slot 2

PCI Slot 3

GNT#A for debug only

J9 must be furthest from the processor.

2 and 3

PCI Connectors

SERIRQ for debug only

REQ#A for debug only

No Stuff R110.

PCI_TEST for debug only

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Intel VC820 Design Guide - Page 184

and 3, PCI Connectors, TITLE: INTELR 820 CHIPSET - FCPGA

Page 184 highlights