Intel VC820 Design Guide - Page 229
Vcc5_db25_cr, Par_init#_r
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8 7 Parallel Port D SLCT 14 PE 14 BUSY 14 C ACK# 14 PDR[7:0] 14 SLIN# 14 PAR_INIT# 14 ERR# 14 B AFD# 14 STB# 14 6 5 4 3 2 RP4 2.2K RP3 2.2K RP2 2.2K RP1 2.2K VCC5 CR1 1 3 MMBD914LT1 VCC5_DB25_CR 5678 4321 5678 4321 5678 5678 4321 4321 R40 2.2K PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 RP19 1 8 2 7 3 6 4 5 RP18 33 1 8 2 7 3 6 4 5 33 PDR7_R PDR6_R PDR5_R PDR4_R PDR3_R PDR2_R SLIN#_R PAR_INIT#_R PDR1 PDR0 RP20 8 1 7 2 6 3 5 4 33 PDR1_R PDR0_R AFD#_R STB#_R J6 DB25_DB9_STK P13 P25 P12 P24 P11 P23 P10 P22 P9 P21 P8 P20 P7 P19 P6 P18 P5 P17 P4 P16 P3 P15 P2 P14 P1 1 D C B 180PF 18 180PF 36 180PF 18 180PF 36 180PF 18 180PF 36 1 CP2 3 CP2 CP5 180PF CP5 27 180PF CP4 45 180PF CP4 27 180PF CP3 45 180PF CP3 27 8 180PF 45 180PF 6 180PF 2 CP2 180PF C81 4 CP2 CP5 CP5 CP4 CP4 CP3 CP3 7 180PF 5 180PF A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PARALLEL PORT 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 26 OF 38 8 7 6 5 4 3 2 1