Home » Intel Manuals » Motherboards » Intel VC820 » Manual Viewer

Intel VC820 Design Guide - Page 211

Title: Intelr 820 Chipset Dual Processor Customer Reference Board

Add to My Manuals
Save this manual to your list of manuals

Page 211 highlights

8 10 MCH HUBREF C194 21 0.01UF 3,5 D HD#[63:0] C B A HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 7 CONN_AGPREF C155 0.1UF U10 MCH_096 R2 R1 R4 P5 T1 R5 V1 Y2 W1 U1 T2 Y3 W2 U3 Y1 U2 W4 W3 V4 U4 T3 Y4 Y5 T4 V5 T5 Y6 W5 U6 V6 W6 T6 W7 U7 Y8 Y7 T8 W8 T7 W9 U8 W10 Y10 V8 U9 Y9 W11 T9 Y11 T10 T12 U10 V10 W12 T11 U13 Y13 Y12 W14 U11 U12 Y14 V14 W13 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 6 HOST 8 7 6 VCC1_8;D4,E6,F6,G6,E7,R6,R7,E8,E9,D10,D11,E12 VCC1_8;E13,E14,F14,T14,E15,P15,B17,C17,C19 VDDQ;F15,R15,J17,L17,N17,T17 GND;A1,A3,G3,J3,L3,N3,R3,V3,B4,D5,L5,U5,B6,D6,D7,V7,B8,D8 GND;D9,J9,K9,L9,M9,V9,B10,J10,K10,L10,M10,C11,J11,K11,L11 GND;M11,V11,C12,D12,J12,K12,L12,M12,B13,D13,V13,T13,D14 GND;B15,D15,B16,D16,E16,F16,A17,E18,V18,A19,H19,K19,M19 GND;P19,T19,D20 C3 GTLREFA V12 GTLREFB E11 RAMREFA E10 RAMREFB U14 AGPREF E20 HUBREF 5 4 3 RAMREF_R GTLREF2 8 R168 RAMREF 8,13 100-1% C191 C203 GTLREF1 8 2 VTT1_5 1 VTT1_5 0.1UF 0.1UF R143 75-1% R131 75-1% HOST HA#3 J1 HA#4 H3 HA#5 H4 HA#6 G5 HA#7 K2 HA#8 H5 HA#9 H2 HA#10 J4 HA#11 L1 HA#12 J5 HA#13 K1 HA#14 J2 HA#15 K5 HA#16 K3 HA#17 L4 HA#18 K4 HA#19 L2 HA#20 N2 HA#21 M3 HA#22 M2 HA#23 M1 HA#24 N5 HA#25 M4 HA#26 P1 HA#27 N1 HA#28 P2 HA#29 P3 HA#30 N4 HA#31 M5 CPURST# P4 ADS# D2 BNR# F5 BPRI# G1 DBSY# D1 DEFER# F2 DRDY# F1 HIT# D3 HITM# E1 HLOCK# F3 HTRDY# F4 RS#0 E5 RS#1 C1 RS#2 E2 HREQ#0 H1 HREQ#1 G4 HREQ#2 E4 HREQ#3 E3 HREQ#4 G2 HCLKIN V2 RSTIN# F20 HLCOMP A18 TEST/GRCOMP T15 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#[31:0] 3,5 R130 150-1% R149 1K-1% C182 R153 80.6-1% GTLREF2 C158 D GTLREF1 C183 R144 150-1% 0.001UF 0.001UF VDDQ C187 470PF MCH_AGPREF_CV R160 80.6-1% R154 1K-1% C MCH_AGPREF 21 470PF MCH_AGPREF_CG CPURST# HADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HTRDY# RS#0 RS#1 RS#2 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 RS#[2:0] 3,5 HREQ#[4:0] 3,5 VCC1_8 R181 562-1% R190 162-1% Place MCH_AGPREF circuit near the MCH. VCC1_8 B RAMREF 8,13 R180 40.2-1% MCHCLK 7 PCIRST# 10,12,13,14,18,21,22,23,24 MCH_HLCOMP A GRCOMP R129 40.2-1% Place R129 and R180 less than 0.5" from MCH using 10 mil trace. 5 4 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: MCH 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-30-1999_10:02 8 OF 38 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-30-1999_10:02

MCH

HD#[63:0]

3,5

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#12

HD#13

HD#14

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#63

HD#62

GRCOMP

MCH_HLCOMP

PCIRST#

10,12,13,14,18,21,22,23,24

MCHCLK

3,5

HREQ#[4:0]

HREQ#4

HREQ#3

HREQ#2

HREQ#1

HREQ#0

RS#[2:0]

3,5

RS#2

RS#1

RS#0

HTRDY#

4,6

HLOCK#

4,6

HITM#

4,6

HIT#

4,6

DRDY#

4,6

DEFER#

4,6

DBSY#

4,6

BPRI#

4,6

BNR#

4,6

HADS#

4,6

CPURST#

4,6

3,5

HA#[31:0]

HA#3

HA#4

HA#5

HA#6

HA#7

HA#30

HA#31

HA#29

HA#28

HA#27

HA#26

HA#25

HA#24

HA#23

HA#22

HA#21

HA#20

HA#19

HA#18

HA#17

HA#16

HA#15

HA#14

HA#13

HA#12

HA#11

HA#10

HA#9

HA#8

HUBREF

CONN_AGPREF

RAMREF_R

GTLREF2

GTLREF1

MCH_AGPREF_CV

R143

75-1%

RAMREF

8,13

R190

162-1%

RAMREF

8,13

100-1%

R168

40.2-1%

R180

MCH_AGPREF_CG

40.2-1%

R129

R131

75-1%

150-1%

R130

R144

150-1%

0.1UF

C155

0.1UF

C191

0.1UF

C203

C158

0.001UF

C182

470PF

562-1%

R181

0.001UF

C183

C187

470PF

U10

V12

E11

E10

U14

E20

T15

A18

F20

W13

V14

Y14

U12

U11

W14

Y12

Y13

U13

T11

W12

V10

U10

T12

T10

Y11

W11

Y10

W10

GTLREF2

GTLREF1

1K-1%

R154

1K-1%

R149

R153

80.6-1%

R160

80.6-1%

MCH_AGPREF

0.01UF

C194

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VDDQ

VCC1_8

VTT1_5

VCC1_8

VDDQ;F15,R15,J17,L17,N17,T17

MCH_096

GND;D9,J9,K9,L9,M9,V9,B10,J10,K10,L10,M10,C11,J11,K11,L11

GND;P19,T19,D20

GND;B15,D15,B16,D16,E16,F16,A17,E18,V18,A19,H19,K19,M19

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#13

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#62

HD#63

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#10

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#29

HA#30

HA#31

CPURST#

ADS#

BNR#

BPRI#

DBSY#

DEFER#

DRDY#

HIT#

HITM#

HLOCK#

HTRDY#

RS#0

RS#1

RS#2

HREQ#0

HREQ#1

HREQ#2

HREQ#3

HREQ#4

RSTIN#

HUBREF

AGPREF

RAMREFB

RAMREFA

GTLREFB

GTLREFA

HD#12

HD#14

HCLKIN

TEST/GRCOMP

HLCOMP

VCC1_8;D4,E6,F6,G6,E7,R6,R7,E8,E9,D10,D11,E12

VCC1_8;E13,E14,F14,T14,E15,P15,B17,C17,C19

GND;A1,A3,G3,J3,L3,N3,R3,V3,B4,D5,L5,U5,B6,D6,D7,V7,B8,D8

GND;M11,V11,C12,D12,J12,K12,L12,M12,B13,D13,V13,T13,D14

HOST

Place R129 and R180 less than 0.5" from MCH using 10 mil trace.

Place MCH_AGPREF circuit near the MCH.

MCH