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Intel VC820 Design Guide - Page 170

Intel VC820 - Desktop Board Motherboard Manual

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8 MCH D C B VCC1_8 0.1UF 0.1UF 0.1UF A 0.1UF No stuff. For test only. 8 C362 C360 C359 C361 7 6 5 GAD[31:0] 19 GC/BE#[3:0] 19 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GC/BE#0 GC/BE#1 GC/BE#2 GC/BE#3 19,32 19,32 19,32 19,32 19,32 19,32 19,32 19,32 19,32 5 19,32 19,32 19 19,32 19,32 19,32 19,32 19,32 19,32 GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# MCH_CLK66 RBF# WBF# ST0 ST1 ST[2:0] ST2 ADSTB0 ADSTB#0 ADSTB1 ADSTB#1 SBSTB SBSTB# U10 MCH_096 F17 G_AD0 G18 G_AD1 G17 G_AD2 G19 G_AD3 G16 G_AD4 G20 G_AD5 H17 G_AD6 H18 G_AD7 J20 G_AD8 J16 G_AD9 K17 G_AD10 K18 G_AD11 J18 G_AD12 L19 G_AD13 K20 G_AD14 L18 G_AD15 M17 G_AD16 P18 G_AD17 M16 G_AD18 P17 G_AD19 N16 G_AD20 P20 G_AD21 P16 G_AD22 R20 G_AD23 T20 G_AD24 R17 G_AD25 U17 G_AD26 T16 G_AD27 U18 G_AD28 T18 G_AD29 U20 G_AD30 U19 G_AD31 H16 G_C/BE#0 L20 G_C/BE#1 N18 G_C/BE#2 R16 G_C/BE#3 L16 N19 N20 M20 M18 K16 U15 Y16 W16 G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# PIPE# W18 CLK66 V16 RBF# V15 WBF# W15 ST0 Y15 ST1 Y17 ST2 J19 AD_STB0 H20 AD_STB#0 R18 AD_STB1 R19 AD_STB#1 Y20 SB_STB Y19 SB_STB# AGP 7 6 5 4 3 2 1 HUB MEMORY AGP HL0 F19 HL1 F18 HL2 E17 HL3 E19 HL4 B20 HL5 B19 HL6 B18 HL7 A20 HL8 D17 HL9 C18 HL10 D18 HL_STB D19 HL_STB# C20 RCLKOUT B1 HCLKOUT A2 DQA0 A13 DQA1 C13 DQA2 A14 DQA3 C14 DQA4 B14 DQA5 C15 DQA6 A15 DQA7 C16 DQA8 A16 DQB0 C7 DQB1 B7 DQB2 C6 DQB3 A6 DQB4 C5 DQB5 A5 DQB6 B5 DQB7 A4 DQB8 C4 RQ0 A7 RQ1 C8 RQ2 A8 RQ3 C9 RQ4 B9 RQ5 A9 RQ6 A10 RQ7 C10 CTM B11 CTM# A11 CFM A12 CFM# B12 CMD B3 SCK B2 SIO C2 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 W20 V17 Y18 W17 V20 W19 V19 U16 4 HL[10:0] HL0 8 HL1 HL2 HL3 D HL4 HL5 HL10 R209 SEL133/100# HL6 7,8,37 4,5 8.2K HL7 HL8 HL9 HL10 R227 8.2K HL_STB 8,37 HL_STB# 8,37 RCLKOUT HCLKOUT LDQA0 LDQA1 LDQA2 LDQA3 LDQA4 LDQA5 LDQA6 LDQA7 LDQA8 5 5 LDQA[8:0] VCC3_3SBY 11 VCC3_3SBY 14 R248 4.7K 9,16,29,31 PWROK U14 VCC 13 12 GND SN74LVC07A PWROK_CTRL C 7 7 MMBT3904LT1 LDQB0 LDQB1 LDQB2 LDQB3 LDQB4 LDQB5 LDQB6 LDQB7 LDQB8 LDQB[8:0] 11 LSCK and LCMD must neck down to 5 mils for 175 mils at Q10 and Q9 attach points. Place Q10 and Q9 as close as possible to MCH. VCC5SBY LCOL[4:0] LCOL0 11 LCOL1 LCOL2 LCOL3 LCOL4 LROW[2:0] LROW0 11 LROW1 LROW2 LCLKTM 11 LCLKTM# 11 LCLKFM 11 LCLKFM# 11 LSCK 11 4.7K B C Q10 SCK_CTRL 3 1B 2 E 7 Q14 C 3 PWROK_CTRL B 1 2 MMBT3904LT1 E LCMD 11 R346 LSIO SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 3 MMBT3904LT1 SBA[7:0] 11 19 Q9 C 3 B1 2 E A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD MCH R PCD PLATFORM DESIGN DRAWN BY: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11-18-1999_11:34 2 1 REV: 1.01 PROJECT: SHEET: 7 OF 36

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-18-1999_11:34

MCH

C360

0.1UF

C359

C361

0.1UF

C362

4.7K

R248

PWROK

9,16,29,31

U14

LCMD

LSCK

SCK_CTRL

HL10

7,8,37

GAD1

GAD2

GAD3

GAD4

GAD5

GAD6

GAD7

GAD8

GAD9

GAD10

GAD11

GAD12

GAD13

GAD14

GAD15

GAD16

GAD17

GAD18

GAD19

GAD20

GAD21

GAD22

GAD23

GAD24

GAD25

GAD26

GAD27

GAD28

GAD29

GAD30

GAD31

GAD[31:0]

GAD0

HL2

HL1

HL[10:0]

HL0

HL10

HL9

HL8

HL7

HL6

HL5

HL4

HL3

HL_STB

8,37

HL_STB#

8,37

LCLKFM#

LCLKFM

LCLKTM#

LCLKTM

LDQB0

LDQB[8:0]

LDQB1

LDQB2

LDQB3

LDQB4

LDQB5

LDQB6

LDQB7

LDQB8

LCOL0

LCOL[4:0]

LCOL1

LCOL2

LCOL3

LCOL4

LROW[2:0]

LROW0

LROW1

LROW2

LDQA6

LDQA7

LDQA8

LDQA4

LDQA3

LDQA2

LDQA1

LDQA0

LDQA[8:0]

LDQA5

GC/BE#2

GC/BE#1

GC/BE#0

GC/BE#[3:0]

GC/BE#3

19,32

GTRDY#

19,32

GIRDY#

19,32

GDEVSEL#

19,32

GFRAME#

GPAR

19,32

GSTOP#

SBSTB#

19,32

ADSTB1

19,32

ADSTB0

19,32

WBF#

19,32

PIPE#

19,32

GREQ#

19,32

GGNT#

ST2

ST0

ST1

ST[2:0]

MCH_CLK66

19,32

RBF#

ADSTB#0

19,32

ADSTB#1

19,32

SBSTB

19,32

HCLKOUT

RCLKOUT

SBA[7:0]

SBA1

SBA3

SBA4

SBA5

SBA6

SBA7

SBA2

SBA0

LSIO

4,5

SEL133/100#

R209

8.2K

Q10

MMBT3904LT1

4.7K

R346

MMBT3904LT1

Q14

MMBT3904LT1

8.2K

R227

PWROK_CTRL

U10

Y19

Y20

W17

Y18

W18

A16

F19

C16

A15

C15

B14

C14

A14

C13

A13

C20

D19

D18

C18

D17

A20

B18

B19

B20

E19

E17

F18

A10

C10

B11

A11

A12

B12

W20

V17

V20

W19

V19

U16

R19

R18

H20

J19

Y17

Y15

W15

V15

V16

W16

Y16

U15

K16

M18

M20

N20

N19

L16

R16

N18

L20

H16

U19

U20

T18

U18

T16

U17

R17

T20

R20

P16

P20

N16

P17

M16

P18

M17

L18

K20

L19

J18

K18

K17

J16

J20

H18

H17

G20

G16

G19

G17

G18

F17

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

1.01

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD

OF 36

VCC1_8

VCC3_3SBY

SN74LVC07A

GND

VCC

VCC5SBY

VCC3_3SBY

MCH_096

HUB

AGP

MEMORY

AGP

G_AD0

G_AD1

G_AD2

G_AD3

G_AD4

G_AD5

G_AD6

G_AD7

G_AD8

G_AD9

G_AD10

G_AD11

G_AD12

G_AD13

G_AD14

G_AD15

G_AD16

G_AD17

G_AD18

G_AD19

G_AD20

G_AD21

G_AD22

G_AD23

G_AD24

G_AD25

G_AD26

G_AD27

G_AD28

G_AD29

G_AD30

G_AD31

G_C/BE#0

G_C/BE#1

G_C/BE#2

G_C/BE#3

G_FRAME#

G_DEVSEL#

G_IRDY#

G_TRDY#

G_STOP#

G_PAR

G_REQ#

G_GNT#

PIPE#

RBF#

WBF#

ST0

ST1

ST2

AD_STB0

AD_STB#0

AD_STB1

AD_STB#1

SBA7

SBA6

SBA5

SBA4

SBA1

SBA0

SIO

SCK

CMD

CFM#

CFM

CTM#

CTM

RQ7

RQ6

RQ2

RQ1

RQ0

HL1

HL2

HL3

HL4

HL5

HL6

HL7

HL8

HL9

HL10

HL_STB

HL_STB#

RCLKOUT

HCLKOUT

DQA0

DQA1

DQA2

DQA3

DQA4

DQA5

DQA6

DQA7

DQB0

DQB1

DQB2

DQB3

DQB4

DQB5

DQB6

DQB7

DQB8

HL0

RQ3

RQ4

RQ5

DQA8

CLK66

SBA2

SBA3

SB_STB

SB_STB#

LSCK and LCMD must neck down to 5 mils for 175 mils at Q10 and Q9 attach points.

Place Q10 and Q9 as close as possible to MCH.

MCH

No stuff. For test only.