Intel
®
820 Chipset Design Guide
iii
Contents
1
Introduction
................................................................................................................
1-1
1.1
About This Design Guide
..............................................................................
1-1
1.2
References
....................................................................................................
1-2
1.3
System Overview
..........................................................................................
1-2
1.3.1
Chipset Components
.......................................................................
1-3
1.3.2
Bandwidth Summary
........................................................................
1-4
1.3.3
System Configuration
.......................................................................
1-5
1.4
Platform Initiatives
.........................................................................................
1-8
1.4.1
Direct Rambus*
................................................................................
1-8
1.4.2
Streaming SIMD Extensions
............................................................
1-8
1.4.3
AGP 2.0
...........................................................................................
1-8
1.4.4
Hub Interface
...................................................................................
1-8
1.4.5
Manageability
...................................................................................
1-9
1.4.6
AC’97
.............................................................................................
1-10
1.4.7
Low Pin Count (LPC) Interface
......................................................
1-11
2
Layout/Routing Guidelines
.........................................................................................
2-1
2.1
General Recommendations
..........................................................................
2-1
2.2
Component Quadrant Layout
........................................................................
2-1
2.3
Intel
®
820 Chipset Component Placement
...................................................
2-3
2.4
Core Chipset Routing Recommendations
.....................................................
2-4
2.5
Source Synchronous Strobing
......................................................................
2-5
2.6
Direct Rambus* Interface
..............................................................................
2-7
2.6.1
Stackup
............................................................................................
2-8
2.6.2
Direct Rambus* Layout Guidelines
..................................................
2-8
2.6.3
Direct Rambus* Reference Voltage
...............................................
2-25
2.6.4
High-speed CMOS Routing
...........................................................
2-25
2.6.5
Direct Rambus* Clock Routing
......................................................
2-28
2.6.6
Direct Rambus* Design Checklist
..................................................
2-28
2.7
AGP 2.0
......................................................................................................
2-31
2.7.1
AGP Interface Signal Groups
.........................................................
2-32
2.7.2
1X Timing Domain Routing Guidelines
..........................................
2-33
2.7.3
2X/4X Timing Domain Routing Guidelines
.....................................
2-33
2.7.4
AGP 2.0 Routing Summary
............................................................
2-35
2.7.5
AGP Clock Routing
........................................................................
2-36
2.7.6
General AGP Routing Guidelines
..................................................
2-36
2.7.7
VDDQ Generation and TYPEDET#
...............................................
2-37
2.7.8
V
REF
Generation for AGP 2.0 (2X and 4X)
....................................
2-39
2.7.9
Compensation
................................................................................
2-41
2.7.10
AGP Pull-ups
.................................................................................
2-41
2.7.11
Motherboard / Add-in Card Interoperability
....................................
2-42
2.8
Hub Interface
..............................................................................................
2-43
2.8.1
Data Signals
...................................................................................
2-44
2.8.2
Strobe Signals
................................................................................
2-44
2.8.3
HREF Generation/Distribution
.......................................................
2-44
2.8.4
Compensation
................................................................................
2-45