Intel VC820 Design Guide - Page 180
Enable, Disable, No stuff JP1, JP3, JP4, R60, R73, R78.
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8 7 LAN D 6 5 4 VCC3_3 3 2 VCC3_3 1 D R73 330 R78 330 R60 330 SPEED_J JP4 ACT_J LI_J R61 LI_CR 330 R64 ACT_CR 330 TD_C TDP 16 Place termination resistors close to 82559. R26 49.9-1% J2 JP3 JP1 No stuff JP1,JP3,JP4,R60,R73,R78. TDN 16 R20 49.9-1% 10 TD+ RJMAG 14 12 TD- LILED C 16 RD_C RDP R62 49.9-1% RJ-45 9 RD+ 13 7 RD- 16 LILED 16,17 16,17 16,17 ACTLED SPEEDLED R63 3 RJ-4 16 C No stuff C61, C79. C61 C79 49.9-1% 4 RJ-5 15 ACTLED 16,17 0.1UF 16 0.1UF RDN 5 RJ-7 6 RJ-8 TDC_J 11 TDC 8 RDC 2 TXC 1 RXC 17 SHLD1 18 SHLD2 RJ_7_J RJ4_J TXC_J RDC_J For debug only. Hold LAN in reset. J17 RSMRST# 1 9,31 LAN_RSMRST# 2 16 3 R10 75 RXC_J C31 C78 75 R8 R5 75 R6 75 0.1UF 0.1UF XC_R 82559 LAN J17 B C5 E nable* 1-2 B No stuff C5. C5 must be rated at 1500V. 470PF No stuff C31. Dis able 2-3 A A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: LAN 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11-18-1999_10:48 SHEET: 17 OF 36 8 7 6 5 4 3 2 1