Intel VC820 Design Guide - Page 134
Component Placement and Interconnection Layout Requirements, 4.2.1 14.318MHz Crystal to CK133
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Clocking 4.2 Component Placement and Interconnection Layout Requirements Detailed explanation of layout requirements for each interconnections are provided in the following sections: • Crystal to CK133 • CK133 to DRCG • MCH to DRCG • DRCG to RDRAM channel 4.2.1 14.318 MHz Crystal to CK133 The distance between the crystal and the CK133 should be minimized. The maximum trace length is 500 mils. 4.2.2 CK133 to DRCG • CPU_div2 • VDDIR - Used as a reference for 2.5V signaling Figure 4-3. CK133 to DRCG Routing Diagram 6 mils 6 mils 6 mils 6 mils 6 mils Ground 6 mils VddiR 6 mils Ground CPU_div2 6 mils 6 mils Ground 1.4 mils 4.5 mils Ground/Power Plane 1.4 mils VddIR and CPU_div2 must be routed as shown in Figure 4-3. Note that the VddiR pin can be connected directly to 2.5V near the DRCG if the 2.5V plane extends near the DRCG. However, if a 2.5V trace must be used, it should originate at the CK133 and be routed as shown. 4-6 Intel®820 Chipset Design Guide