Intel VC820 Design Guide - Page 131
Table 4-2. Intel, Chipset Platform Clock Skews, Clock Symbols, See Relationship, Notes
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Clocking Table 4-2. Intel® 820 Chipset Platform Clock Skews Skew Clock Symbols See Figure 4-1 Relationship Pin-to-Pin (ps) Board (ps) Total (ps) Notes Min Max Min Max Min Max A leads C, A leads E (or C leads E) SC242 HCLK to SC242 HCLK (DP ONLY) And SC242 HCLK to MCH HCLK (DP ONLY) -175 A leads E SC242 HCLK to MCH HCLK (UP ONLY) 0 P leads F MCH CLK66 to AGP graphics device 0 AGPCLK L leads another L PCICLK to PCICLK (or L leads H) -500 I leads H ICH CLK66 leads ICH PCICLK +1500 F leads I ICH CLK66 to MCH CLK66 -250 Worst case skew between H, L, M and N Worst case FWHCLK, LPCCLK, PCICLK -500 B leads D, B leads G Processor PICCLK leads Processor PICCLK And Processor PICCLK leads ICH APICCLK -250 +175 0 0 +500 +4000 250 +500 +250 -125 -125 -125 -1500 -500 -125 -1500 -125 +125 +125 +125 +1500 +500 +125 +1500 +125 -300 -125 -125 -2000 +1000 -375 -2000 -375 +300 1, 7 +125 2, 3, 7 +125 4, 8 +2000 +4500 +375 8 +2000 5 +375 6 NOTES: 1. DP Only 2. UP: MCH and CPU clock drivers are tied together to eliminate pin-to-pin skew. -175 and +175 pin-to-pin skew only apply to DP. 3. UP Only 4. Clock drivers tied together to eliminate pin-to-pin skew. 5. The skew between any PCICLK clocks on any two inputs in the system. 6. The skew between any APIC clocks on any two inputs in the system. 7. If SSC is enabled, an additional ±40ps must is added to the pin-to-pin skew 8. If SSC is enabled, an additional ±60ps must is added to the pin-to-pin skew Intel®820 Chipset Design Guide 4-3