Intel VC820 Design Guide - Page 221

Y2 XTAL 25MHZ G14 VSSPL[0] K12 VSSPL[1] P8 VSSPL[2] N12 VSSPL[3] C10 VSSPT B3 VSSPP[0] B7 VSSPP[1] E2 VSSPP[2] K2 VSSPP[3] M6 VSSPP[4] N1 VSSPP[5] D4 VSS[0] D5 VSS[1] D6 VSS[2] D7 VSS[3] D8 VSS[4] D11 VSS[5] E4 VSS[6] E5 VSS[7] E6 VSS[8] E7 VSS[9] E8 VSS[10] E9 VSS[11] E10 VSS[12] E11 VSS[13] F4 VSS[14] F5 VSS[15] F6 VSS[16] F7 VSS[17] F8 VSS[18] F9 VSS[19] F10 VSS[20] F11 VSS[21] G7 VSS[22] G8 VSS[23] G9 VSS[24] G10 VSS[25] G11 VSS[26] H9 VSS[27] H10 VSS[28] H11 VSS[29] L6 VSS[30] L11 VSS[31] 8 7 6 LAN 10,22,23 D AD[31:0] C 10,22,23 C_BE#[3:0] B VCC5SBY 10,22,23,34 10,22,23,34 10,22,23,34 10,22,23,34 10,22,23,34 10,22,23 10,21,22,23,34 10,22,23,34 10,22,23,34 10,18,22,23 10,34 10,34 8,10,12,13,14,21,22,23,24 7 AD20 2 1 A 9,11,31,33 19 11,34 11,34 C101 22PF C96 22PF U5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 N7 AD0 M7 AD1 P6 AD2 P5 AD3 N5 AD4 M5 AD5 P4 AD6 N4 AD7 P3 AD8 N3 AD9 N2 AD10 M1 AD11 M2 AD12 M3 AD13 L1 AD14 L2 AD15 K1 AD16 E3 AD17 D1 AD18 D2 AD19 D3 AD20 C1 AD21 B1 AD22 B2 AD23 B4 AD24 A5 AD25 B5 AD26 B6 AD27 C6 AD28 C7 AD29 A8 AD30 B8 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3 M4 C/BE0# L3 C/BE1# F3 C/BE2# C4 C/BE3# FRAME# F2 IRDY# F1 TRDY# G3 DEVSEL# H3 STOP# H1 PAR J1 PIRQ#A H2 PERR# J2 SERR# A2 R75 AD20_RLAN A4 100 PREQ#3 C3 PGNT#3 J3 PCIRST# C2 PCLK5 G1 FRAME# IRDY# TRDY# DEVSEL# STOP# PAR INTA# PERR# SERR# IDSEL REQ# GNT# RST# CLK PWROK B9 ISOLATE# LAN_RSMRST# A9 ALTRST# ALERTCLK_SBY A10 SMBCLK ALERTDATA_SBY C9 SMBD G2 VIO LAN_X1 N11 X1 LAN_X2 P11 X2 8 7 6 VCCPL[0] G13 VCCPL[1] K13 VCCPL[2] N8 VCCPL[3] P12 VCCPT A11 VCCPP[0] A3 VCCPP[1] A7 VCCPP[2] E1 VCCPP[3] K3 VCCPP[4] N6 VCCPP[5] P2 VCC[0] E12 VCC[1] G5 VCC[2] G6 VCC[3] H5 VCC[4] H6 VCC[5] H7 VCC[6] H8 VCC[7] J5 VCC[8] J6 VCC[9] J7 VCC[10] J8 VCC[11] J9 VCC[12] J10 VCC[13] J11 VCC[14] K4 VCC[15] K5 VCC[16] K6 VCC[17] K7 VCC[18] K8 VCC[19] K9 VCC[20] K10 VCC[21] K11 VCC[22] L4 VCC[23] L5 VCC[24] L9 VCC[25] L10 R59 5 4 82559 5 4 3 2 1 VCC3_3SBY D LILED A12 LILED 19 ACTLED C11 ACTLED 19 SPEEDLED B11 XSRPEFE1D=L1E9D TDP C13 TDP TDN C14 TDN RDP E13 RDP RDN E14 RDN 19 19 19 VCC3_3SBY 19 SMBALRT# B10 CSTSCHG C5 PME# A6 PCI_PME# 10,21,22,23 3.3K FLA0/PCIMODE# J13 FLA1/AUXPWR J12 FLA2 K14 FLA3 L14 FLA4 L13 FLA5 L12 FLA6 M14 FLA7 M13 FLA8/IOCHRDY N14 FLA9/MRST P13 FLA10/MRING# N13 FLA11/MINT M12 FLA12/MCNTSM# M11 FLA13/EEDI P10 FLA14/EEDO N10 FLA15/EESK M10 FLA16 P9 AUXPWR EEDI EEDO EESK C VCC3_3SBY FLD0 F14 FLD1 F13 FLD2 F12 FLD3 G12 FLD4 H14 FLD5 H13 FLD6 H12 FLD7 J14 FLD5 FLD6 U24 93C46 8 3 VCC EEDI 4 EEDO NC2 7 2 EESK NC1 6 1 EECS GND 5 B EECS P7 FLCS# N9 FLOE# M8 FLWE# M9 CLKRUN# C8 TEST A13 TEXEC D13 TCK D14 TI D12 TO B12 EECS No stuff R57, R58 R58 3.3K R57 CLKRUN#_LAN TEST_LAN 3.3K R363 62K R14 3.3K RBIAS10 B14 RBIAS100 B13 VREF C12 RBIAS10 RBIAS100 R16 549 R15 619 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: LAN CONTROLLER 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11-29-1999_14:46 SHEET: 18 OF 38 3 2 1