Intel VC820 Design Guide - Page 58
AGP Interface Signal Groups, Signal groups
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Layout/Routing Guidelines 2.7.1 2-32 AGP Interface Signal Groups The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. However, trace length matching requirements only need to be met within each set of 2X/4X timing domain signals. Signal groups • 1X Timing Domain - CLK (3.3V) - RBF# - WBF# - ST[2:0] - PIPE# - REQ# - GNT# - PAR - FRAME# - IRDY# - TRDY# - STOP# - DEVSEL# • 2X/4X Timing Domain Set #1 - AD[15:0] - C/BE[1:0]# - AD_STB0 - AD_STB0# (used in 4X mode ONLY) Set #2 - AD[31:16] - C/BE[3:2]# - AD_STB1 - AD_STB1# (used in 4X mode ONLY) Set #3 - SBA[7:0] - SB_STB - SB_STB# (used in 4X mode ONLY) • Miscellaneous, Async - USB+ - USB- OVRCNT# - PME# - TYPDET# - PERR# - SERR# - INTA# - INTB# Intel®820 Chipset Design Guide