HP Cluster Platform Interconnects v2010 Quadrics QsNetII Interconnect - Page 34

Creating a Clock Distribution Network

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2. Clock in ports. Clock in A is the top port, Clock in B is the bottom port and is not used. 3. Mode select switch. 4. Power switch. 5. Fuse. 6. Power inlet. By linking two or more clock boxes together, it is possible to provide clock signals for more than 24 interconnects. The QM580 has a 1 U high, 170 mm deep, screened enclosure, suitable for mounting in standard 19 inch (600 mm) equipment racks. The main input current to the QM580 is less than 0.30 A. The unit uses a Universal power supply operating in the range 100-240 VAC (50/60 Hz). Power is supplied through a standard IEC320 inlet. 3.5.1 Creating a Clock Distribution Network You must use clock distribution cables to connect each system interconnect to a single clock distribution box. The shielded CAT-V cables that connect the system interconnects to the clock distribution box are called clock distribution cables. The front panel of the clock distribution box has connections for 25 CAT-V connectors, as shown in Figure 3-9. The ports labelled 0-11 and 12-23 are clock outputs for connection to the system interconnects in a federated configuration. The port labelled CLKIN is not used. Note The front panel legend shows a number next to each CAT-V connector. Connect node-level interconnect 0 to port 0, node-level interconnect 1 to port 1, and so on. Two clock boxes are used to provide signal redundancy. One clock box is always designated as the master clock, and its Master LED must be on. To create the clock distribution network, use the following procedure: 1. Identify the first interconnect enclosure, QR0N00 according to the interconnect naming conventions defined in the cabling tables. 2. Connect one end of the clock distribution cable to the CLK A port on each Quadrics system interconnect, and the other to one of the Cat-V connectors on the front panel of the clock distribution box. Note When connecting clock distribution cables, it is essential that CLK A and CLK B signals are not mixed between system interconnects; you must connect all CLK A ports to one clock distribution box. If you have a backup clock distribution box, you connect all CLK B ports to that box. 3. Referring to the cabling tables, connect the other end of the clock distribution cable to the specified port in the clock box A, the master clock box. 4. Connect a clock distribution cable to the port labelled Pri Clk in the interconnect's controller B card. 5. Referring to the cabling tables, connect the other end of the clock distribution cable to the specified port in the clock box B, the slave (redundant) clock box. 3-10 128-Port Interconnect Modules

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2.
Clock in ports. Clock in A is the top port, Clock in B is the bottom port and
is not used.
3.
Mode select switch.
4.
Power switch.
5.
Fuse.
6.
Power inlet.
By linking two or more clock boxes together, it is possible to provide clock signals
for more than 24 interconnects. The QM580 has a 1 U high, 170 mm deep, screened
enclosure, suitable for mounting in standard 19 inch (600 mm) equipment racks.
The main input current to the QM580 is less than 0.30 A. The unit uses a Universal
power supply operating in the range 100-240 VAC (50/60 Hz). Power is supplied
through a standard IEC320 inlet.
3.5.1 Creating a Clock Distribution Network
You must use clock distribution cables to connect each system interconnect to a
single clock distribution box. The shielded CAT–V cables that connect the system
interconnects to the clock distribution box are called clock distribution cables. The
front panel of the clock distribution box has connections for 25 CAT–V connectors,
as shown in Figure 3-9.
The ports labelled 0–11 and 12–23 are clock outputs for connection to the system
interconnects in a federated configuration. The port labelled CLKIN is not used.
_________________________
Note
_________________________
The front panel legend shows a number next to each CAT–V connector.
Connect node-level interconnect 0 to port 0, node-level interconnect 1
to port 1, and so on.
Two clock boxes are used to provide signal redundancy. One clock box is always
designated as the master clock, and its Master LED must be on. To create the clock
distribution network, use the following procedure:
1.
Identify the first interconnect enclosure, QR0N00 according to the interconnect
naming conventions defined in the cabling tables.
2.
Connect one end of the clock distribution cable to the CLK A port on each
Quadrics system interconnect, and the other to one of the Cat-V connectors on
the front panel of the clock distribution box.
_______________________
Note
_______________________
When connecting clock distribution cables, it is essential that CLK
A and CLK B signals are not mixed between system interconnects;
you must connect all CLK A ports to one clock distribution box. If
you have a backup clock distribution box, you connect all CLK B
ports to that box.
3.
Referring to the cabling tables, connect the other end of the clock distribution
cable to the specified port in the clock box A, the master clock box.
4.
Connect a clock distribution cable to the port labelled Pri Clk in the
interconnect’s controller B card.
5.
Referring to the cabling tables, connect the other end of the clock distribution
cable to the specified port in the clock box B, the slave (redundant) clock box.
3-10
128-Port Interconnect Modules