HP Cluster Platform Interconnects v2010 Quadrics QsNetII Interconnect - Page 94

Verifying the Node Level to Top Level Link

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c. If the green LEDs are still not illuminated, proceed with step 11. 11. Test the node's PCI I/O system, as described in the documentation supplied with the node. If the node's PCI I/O system displays no errors, then the LED array is faulty and you must replace the appropriate components. You have completed the diagnostic process. 10.3.3 Verifying the Node Level to Top Level Link The switch card LEDs are at either end of the link cables that connect the node-level interconnects to the top-level interconnects. All three green LEDs on the end-to-end link must be illuminated when the node has booted and the interconnects have initialized. Note Ignore illuminated red LEDs on connected links when the interconnect is first powered up. These will be cleared by the interconnect manager software. You can also Ignore red LEDs on unconnected links. To clear the LEDs you will use the jtest utility to select and clear the error registers in all components. When you have cleared the registers, examine the LEDs and interpret them as follows: • Ignore any red LEDs on unconnected links. • If the green LED is lit at one end of a link but not the other, it is most likely that the LED array is are faulty. First try replacing the component that is not showing an illuminated green LED. • If the interconnects are powered up and connected to each other and any of the three green LEDs for each link cable are not illuminated, the link is not working and you should use the verification procedure described in this section. Use the following procedure to verify the link between the node and the top-level interconnects. 1. Visually inspect the hardware to ensure that the node level interconnect is correctly connected to the top-level interconnect and that all cards are correctly seated in each interconnect as follows: • Interconnect components are keyed to prevent incorrect insertion, and are latched or screwed down to ensure good connector contact. If a component that is inserted correctly, its bezel will not be aligned with the chassis or with other adjacent components. • Link cables must not deviate more than 10 degrees from horizontal at their connection point with a port. To avoid problems at port connections, ensure that all cables are correctly hooked into the cable management system. 2. Check the LEDs on the switch card in the node-level interconnect and the LEDs on the switch card in the top-level interconnect. If neither of the green LEDs is lit, replace each of the following components with a known good component, or verify the configuration as instructed. Ensure that you perform each stop in the order specified. Check the link LEDs after each step until both LEDs are illuminated, indicating that the link is now working: a. Verify the clock source setting and clock frequency on each interconnect by using the jtest command as specified in Section 11.2. b. If the output from the jtest command reports that the federated interconnect has phase errors, or if the clock speed is not reported to 10-8 Using Component LEDs

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c.
If the green LEDs are still not illuminated, proceed with step 11.
11.
Test the node’s PCI I/O system, as described in the documentation supplied
with the node.
If the node’s PCI I/O system displays no errors, then the LED array is faulty
and you must replace the appropriate components. You have completed the
diagnostic process.
10.3.3 Verifying the Node Level to Top Level Link
The switch card LEDs are at either end of the link cables that connect the
node-level interconnects to the top-level interconnects. All three green LEDs
on the end-to-end link must be illuminated when the node has booted and the
interconnects have initialized.
_________________________
Note
_________________________
Ignore illuminated red LEDs on connected links when the interconnect
is first powered up. These will be cleared by the interconnect manager
software. You can also Ignore red LEDs on unconnected links.
To clear the LEDs you will use the
jtest
utility to select and clear the error
registers in all components. When you have cleared the registers, examine the
LEDs and interpret them as follows:
•
Ignore any red LEDs on unconnected links.
•
If the green LED is lit at one end of a link but not the other, it is most likely
that the LED array is are faulty. First try replacing the component that is not
showing an illuminated green LED.
•
If the interconnects are powered up and connected to each other and any of
the three green LEDs for each link cable are not illuminated, the link is not
working and you should use the verification procedure described in this section.
Use the following procedure to verify the link between the node and the top-level
interconnects.
1.
Visually inspect the hardware to ensure that the node level interconnect is
correctly connected to the top-level interconnect and that all cards are correctly
seated in each interconnect as follows:
•
Interconnect components are keyed to prevent incorrect insertion, and are
latched or screwed down to ensure good connector contact. If a component
that is inserted correctly, its bezel will not be aligned with the chassis or
with other adjacent components.
•
Link cables must not deviate more than 10 degrees from horizontal at their
connection point with a port. To avoid problems at port connections, ensure
that all cables are correctly hooked into the cable management system.
2.
Check the LEDs on the switch card in the node-level interconnect and the
LEDs on the switch card in the top-level interconnect. If neither of the green
LEDs is lit, replace each of the following components with a known good
component, or verify the configuration as instructed. Ensure that you perform
each stop in the order specified. Check the link LEDs after each step until both
LEDs are illuminated, indicating that the link is now working:
a.
Verify the clock source setting and clock frequency on each interconnect
by using the
jtest
command as specified in Section 11.2.
b.
If the output from the
jtest
command reports that the federated
interconnect has phase errors, or if the clock speed is not reported to
10-8
Using Component LEDs