Intel 925 Data Sheet

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Manual

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  • Intel 925 | Data Sheet - Page 1
    R Intel® 925X/925XE Express Chipset Datasheet For the Intel® 82925X/82925XE Memory Controller Hub (MCH) November 2004 Document Number: 301464-003
  • Intel 925 | Data Sheet - Page 2
    and before placing your product order. Ω Look for systems with the Intel® Pentium® 4 Processor with HT Technology logo and also including an Intel® 925, 915, or 910 Express Chipset (see the product spec sheet or ask your salesperson). Performance and functionality will vary depending on
  • Intel 925 | Data Sheet - Page 3
    3.3.4 PCI Express* Enhanced Configuration Mechanism 40 3.3.5 Intel® 82925X/925XE MCH Configuration Cycle Flowchart 42 3.4 I/O Mapped Registers 43 3.4.1 CONFIG_ADDRESS-Configuration Address Register 43 3.4.2 CONFIG_DATA-Configuration Data Register 44 4 Host Bridge/DRAM Controller Registers (D0
  • Intel 925 | Data Sheet - Page 4
    MCHBAR-MCH Memory Mapped Register Range Base Address (D0:F0 55 PCIEXBAR-PCI Express* Register Intel® 82925X Only)... 59 DERRSYN-DRAM Error Syndrome (D0:F0) (Intel® 82925X Only) .... 60 DERRDST-DRAM Error Destination (D0:F0) (Intel 5.1.10 C0DRC0-Channel A DRAM Controller Mode 0 88 5.1.11 C1DRB0-
  • Intel 925 | Data Sheet - Page 5
    -DMI VC1 Resource Status 106 7.1.11 DMILCAP-DMI Link Capabilities 106 7.1.12 DMILCTL-DMI Link Control 107 7.1.13 DMILSTS-DMI Link Status 107 8 Host-PCI Express* Graphics Bridge Registers (D1:F0 109 8.1 Device 1 Configuration Register Details 112 8.1.1 VID1-Vendor Identification (D1:F0
  • Intel 925 | Data Sheet - Page 6
    :F0 132 MA-Message Address (D1:F0 133 MD-Message Data (D1:F0 133 PEG_CAPL-PCI Express* Capability List (D1:F0 134 PEG_CAP-PCI Express*-G Capabilities (D1:F0 134 DCAP-Device Capabilities (D1:F0 135 DCTL-Device Control (D1:F0 136 DSTS-Device Status (D1:F0 137 LCAP-Link Capabilities (D1:F0 138
  • Intel 925 | Data Sheet - Page 7
    168 9.4.4 SMM Control Combinations 169 9.4.5 SMM Space Decode and Transaction Handling 169 9.4.6 Processor WB Transaction to an Enabled SMM Address Space ...... 169 9.4.7 SMM Access through GTT TLB 170 9.4.8 Memory Shadowing 170 9.4.9 I/O Address Space 170 9.4.10 PCI Express* I/O Address
  • Intel 925 | Data Sheet - Page 8
    R 13 Testability ...221 13.1 Complimentary Pins 221 13.2 XOR Test Mode Initialization 222 13.3 XOR Chain Definition 222 13.4 XOR Chains...222 13.5 Pads Excluded from XOR Mode(s 242 8 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 9
    Diagram 22 Figure 3-1. Conceptual Intel® 925X/925XE Express Chipset Platform PCI Configuration Diagram 37 Figure 3-2. DMI Type 0 Configuration Address Translation 39 Figure 3-3. DMI Type 1 Configuration Address Translation 40 Figure 3-4. Memory Map to PCI Express* Device Configuration Space 41
  • Intel 925 | Data Sheet - Page 10
    SMM Control Table 169 Table 10-1. Sample System Memory Organization with Interleaved Channels 175 Table 10-2. Sample System Memory Organization with Asymmetric Channels 175 Table 10-3. DDR2 DIMM Supported Configurations 178 Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric
  • Intel 925 | Data Sheet - Page 11
    R Revision History Revision -001 -002 -003 Description • Initial Release • Added Intel® Extended Memory 64 Technology (Intel® EM64T) Support Information • Added 82925XE MCH Product Information Date June 2004 August 2004 November 2004 § Intel® 82925X/82925XE MCH Datasheet 11
  • Intel 925 | Data Sheet - Page 12
    a Cache Line Size of 64 bytes ⎯ Suspend-to-RAM support using CKE ⎯ Supports Intel Pentium® 4 processors with ⎯ Supports configurations defined in the Intel® EM64T Φ JEDEC DDR2 DIMM specification only ƒ DMI Interface ƒ PCI Express Graphics Interface ⎯ A chip-to-chip connection interface to
  • Intel 925 | Data Sheet - Page 13
    Introduction R 1 Introduction The Intel® 925X Express chipset and Intel® 925XE Express chipset are designed for use with the Intel® Pentium® 4 processor in entry-level, uniprocessor, workstation platforms. The chipsets contain two components: 82925X or 82925XE Memory Controller Hub (MCH) for the
  • Intel 925 | Data Sheet - Page 14
    R Figure 1-1. Intel® 925X/925XE Express Chipset System Block Diagram Example Display Intel® Pentium® 4 Processor 200/266 MHz FSB (800/1066 MT/s) Intel® 925X/925XE Express Chipset Graphics Card PCI Express x16 Graphics Intel® 82925X MCH/ Intel® 82925XE MCH System Memory Channel A DDR2
  • Intel 925 | Data Sheet - Page 15
    called DMI. The Memory Controller Hub (MCH) component contains the processor interface and DRAM controller. It may also contain an x16 PCI Express port (typically the external graphics interface). It communicates with the I/O controller hub (ICH6*) and other I/O controller hubs over the DMI
  • Intel 925 | Data Sheet - Page 16
    transactions. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports one or two channels of DDR2 SDRAM. The MCH also supports the new PCI Express based external graphics attach. Thus, the 925X/925XE Express chipset is not
  • Intel 925 | Data Sheet - Page 17
    1.9 V for DDR2 533 MHz CL3-3-3. • Supports non-ECC and ECC (925X only) memory. • Supports 256-Mb, 512-Mb and 1-Gb DDR2 technologies • Supports only x8, x16, DDR2 devices with four banks and also supports eight bank, 1-Gbit DDR2 devices. • Supports opportunistic refresh • In dual channel mode the MCH
  • Intel 925 | Data Sheet - Page 18
    -speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true Express Graphics Attach). • 32-bit downstream addressing • APIC and MSI interrupt messaging support. Will send Intel-defined "End Of Interrupt" broadcast message when initiated by the processor
  • Intel 925 | Data Sheet - Page 19
    (1)x16. • PCI Express Graphics Extended Configuration Space. The support includes: • Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms. • Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI ⎯ MSIs routed directly to FSB ⎯ From I/OxAPICs Intel
  • Intel 925 | Data Sheet - Page 20
    . The PCI Express core clock of 250 MHz is generated from a separate PCI Express PLL. This graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by processor) • ACPI Rev 1.0 compatible power management • Supports processor states: C0, C1, C2, C3, and C4 • Supports
  • Intel 925 | Data Sheet - Page 21
    , and supports VTT of from 0.83 V to 1.65 V (including guardbanding). PCIE PCI-Express interface signals. These signals are compatible with PCI Express 1.0 Signaling Analog reference or output. May be used as a threshold voltage or for buffer compensation. Intel® 82925X/82925XE MCH Datasheet 21
  • Intel 925 | Data Sheet - Page 22
    Express x16 Graphics Port Processor System Bus Interface Clocks, Reset, and Misc. Direct Media Interface System Memory DDR2 Channel A System Memory DDR2 Channel B Voltage Reference, and Power System Memory 1. SCB_A[7:0] and SCB_B[7:0] are on the Intel® 82925X only. 2. SDQS_A8/SDQS_A8# and SDQS_B8/SDQS_B8
  • Intel 925 | Data Sheet - Page 23
    has been satisfied. CPU Reset: The HCPURST# pin is an output from the MCH. The MCH asserts HCPURST# while RSTIN# is asserted and for approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows the processors to begin execution in a known state. Note that the Intel® ICH6 must provide
  • Intel 925 | Data Sheet - Page 24
    PCI Express Graphics accesses to DRAM are allowed when HLOCK# is asserted by the processor). Precharge Request: The processor provides a "hint" to the MCH that it is OK to close the DRAM page of the memory read provided in both halves of the request phase. 24 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 25
    information to define the complete transaction type. The transactions supported by the MCH Host Bridge are defined in the Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. Response Intel® 82925X/82925XE MCH Datasheet 25
  • Intel 925 | Data Sheet - Page 26
    SDRAM components during the active state. There is one chip select for each SDRAM rank. Memory Address: These signals are used to provide the multiplexed row and column address to the On Die Termination: Active On-die Termination Control signals for DDR2 devices. Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 27
    SDRAM components during the active state. There is one chip select for each SDRAM rank Memory Address: These signals are used to provide the multiplexed row and column address to the Die Termination: Active On-die Termination Control signals for DDR2 devices. Intel® 82925X/82925XE MCH Datasheet 27
  • Intel 925 | Data Sheet - Page 28
    System Memory RCOMP I/O DDR2 On-Die DRAM Over Current Detection (OCD) driver A PCI Express Graphics Receive Differential Pair PCI Express Graphics Transmit Differential Pair PCI Express Graphics Output MCH's PCI Express lane numbers are reversed 1 = Normal operation 28 Intel® 82925X/82925XE
  • Intel 925 | Data Sheet - Page 29
    the clocks necessary for the support of PCI Express. Display PLL Differential Clock In Reset In: When asserted, this signal will asynchronously reset the MCH logic. This signal is connected to the PLTRST# output of the Intel® ICH6. All PCI Express Graphics Attach output signals will also tri
  • Intel 925 | Data Sheet - Page 30
    V 1.5 V 1.5 V 0 V Description Core Power. Processor System Bus Power. PCI Express* and DMI Power. System Memory Power. DDR2: VCCSM = 1.8 V (VCCSM influence (such as external pull-up/pull-down resistors or external drivers). Legend: CMCT: DRIVE: TERM: LV: HV: IN: Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 31
    ) TRI (No VTT) TRI (No VTT) TRI (No VTT) TRI TRI TRI Pull-up/ Pull-down 20 Ω resistor for board with target impedance of 60 Ω Intel® 82925X/82925XE MCH Datasheet 31
  • Intel 925 | Data Sheet - Page 32
    Reset and S3 States Interface Signal Name System Memory System Memory Channel A SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0]1 SDQS_A[8:0] TRI LV TRI LV TRI TRI TRI TRI TRI TRI TRI TRI 32 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 33
    the 82925X MCH only. Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States Interface Signal Name PCI Express*Graphics EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15 V CMCT CMCT CMCT 1.0 V CMCT 1.0 V S3 CMCT CMCT CMCT 1.0 V CMCT 1.0 V Pull-up/ Pulldown Intel® 82925X/82925XE MCH Datasheet 33
  • Intel 925 | Data Sheet - Page 34
    IN IN IN IN IN IN S3 IN HV PU TRI TERM HV TERM HV PU Pull-up/ Pull-down Pull-up/ Pull-down 34 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 35
    processor I/O address space: Control registers and internal configuration registers. • Control registers are I/O mapped into the processor I/O space that control access to PCI and PCI Express 4095 of each device may only be accessed using memory mapped transactions in DWord (32-bit) quantities.
  • Intel 925 | Data Sheet - Page 36
    within a register, the MCH contains address locations in the configuration space of the Host Bridge entity that are marked either "Reserved" or "Intel Reserved". The MCH responds to accesses to "Reserved" address locations by completing the host cycle. When a "Reserved" register location is read
  • Intel 925 | Data Sheet - Page 37
    is shown in Figure 3-1. Figure 3-1. Conceptual Intel® 925X/925XE Express Chipset Platform PCI Configuration Diagram Processor PCI Configuration Window in I/O Space Intel® 82925X/82925XE MCH PCI Express* Bus 0, Device 1 DRAM Controller Interface Bus 0, Device 0 DMI PCI Configuration Window
  • Intel 925 | Data Sheet - Page 38
    to the Intel ICH6 via DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port. A detailed description of the mechanism for translating processor I/O bus
  • Intel 925 | Data Sheet - Page 39
    the processor's I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers, DMI, or PCI Express. 3.3.2 bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of the Intel ICH6's devices, the DMI, or a downstream PCI bus.
  • Intel 925 | Data Sheet - Page 40
    the DWord to be accessed. Locked transactions to the PCI Express memory mapped configuration address space are not supported. All changes made using either access mechanism are equivalent. The Requests, the Extended Register Address field must be all zeros. 40 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 41
    posted on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes). See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI Express enhanced configuration mechanism and transaction rules. Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 42
    Register Description R 3.3.5 Intel® 82925X/925XE MCH Configuration Cycle Flowchart Figure 3-5. Intel® 82925X/82925XE MCH Configuration Cycle Flowchart DW I/O Write to CONFIG_ADDRES S with bit 31 = 1 I/O Read/Write to CONFIG_DATA MCH Generates Type 1 Access to PCI Express Yes Bus# = 0 No Yes Bus# >
  • Intel 925 | Data Sheet - Page 43
    MCH contains two registers that reside in the processor I/O address space − the Configuration Address ( Express Graphics. This field is mapped to byte 8 [7:0] of the request header format during PCI Express Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles. Intel
  • Intel 925 | Data Sheet - Page 44
    . The MCH is always Device Number 0 for the Host bridge entity, Device Number 1 for the Host-PCI Express entity. Therefore, when the Bus Number =0 and the Device Number equals 0, 1, or 2 the internal MCH devices , and offset of the register to be accessed. § 44 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 45
    F0) R 4 Host Bridge/DRAM Controller Registers (D0:F0) The DRAM Controller registers are in Device 0 (D0), Base Address MCH Memory Mapped Register Range Base Address PCI Express* Register Range RO RO - R/W/O R/W/O - RO - RO R/W E0000000h R/W 00000000h R/W Intel® 82925X/82925XE MCH Datasheet 45
  • Intel 925 | Data Sheet - Page 46
    Access Control Reserved Top of Low Usable DRAM System Management RAM Control 9Eh ESMRAMC Extended System Management RAM Control 9F- RO/S - R/W R/W R/W R/W R/W R/W R/W R/W - R/W RO, R/W/L RO, R/W/L - RO, R/W/L R/W R/W R/W - R/W RO - R/W R/W R/W R/W - R/W 46 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 47
    Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 00000000h 00000000h Access R/W - R/W - R/W - R/W - R/W, RO - R/W R/W R/W R/W - R/W R/W - R/W - R/W - R/W, RO - R/W, RO - R/W R/W/C/S Intel® 82925X/82925XE MCH Datasheet 47
  • Intel 925 | Data Sheet - Page 48
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1 4.1.1 4.1.2 Device 0 Function 0 PCI Configuration Register Details VID-Vendor Identification (D0:F0) Number (DID): This field is an identifier assigned to 2580h the MCH core/primary PCI device. 48 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 49
    control bits are used in a logical OR manner to enable the SERR DMI message mechanism. Address/Data Stepping Enable (ADSTEP). Hardwired to 0. Parity Error Enable (PERRE). PERR# is not implemented by the MCH and this bit is hardwired to 0. VGA Palette Snoop Enable (VGASNOOP). Hardwired to a 0. Memory
  • Intel 925 | Data Sheet - Page 50
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.4 PCISTS-PCI Status (D0:F0 by the MCH. 6 Reserved 5 RO 66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0. 0b 4 RO Capability List (CLIST): This bit is hardwired to . 3:0 Reserved 50 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 51
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.5 4.1.6 RID-Revision Identification (D0:F0) PCI the 00h revision identification number for the MCH Device 0. See Intel® 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register. CC-Class Code
  • Intel 925 | Data Sheet - Page 52
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.7 4.1.8 4.1.9 MLT-Master Latency Timer (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 0Dh 00h the vendor of the system board. After it has been written once, it becomes read only. 52 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 53
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.10 SID-Subsystem Identification (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 block: In this case the E0h first capability is the product-specific Capability Identifier (CAPID0). Intel® 82925X/82925XE MCH Datasheet 53
  • Intel 925 | Data Sheet - Page 54
    Controller Registers (D0:F0) R 4.1.12 EPBAR-Egress Port Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 40h 00000000h RO 32 bits This is the base address for the Egress Port MMIO configuration space. There is no physical memory 2.3 compliant memory mapped space.
  • Intel 925 | Data Sheet - Page 55
    DRAM Controller Registers (D0:F0) R 4.1.13 MCHBAR-MCH Memory Mapped Register Range Base Address (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 44h 00000000h R/W 32 bits This is the base address for the MCH memory-mapped configuration space. There is no physical memory within
  • Intel 925 | Data Sheet - Page 56
    field corresponds to bits 31 to 28 of the base address for PCI Express enhanced configuration space. BIOS will program this register resulting in a base address for a 256-MB block of contiguous memory address space. Having control of those particular 4 bits insures that this base address will be on
  • Intel 925 | Data Sheet - Page 57
    Controller Express hierarchy associated with the MCH. There is no physical memory does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is memory address space. This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory
  • Intel 925 | Data Sheet - Page 58
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.16 DEVEN-Device Enable (D0:F0) PCI Device: 0 = EPBAR is disabled and does not claim any memory. 1 = EPBAR memory mapped accesses are claimed and decoded appropriately. 26:2 Reserved 1 R/W PCI Express* Port (D1EN): 1b 0 = Bus 0 Device 1
  • Intel 925 | Data Sheet - Page 59
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.17 DEAP-DRAM Error Address Pointer (D0:F0) (Intel® 82925X Only) PCI Device: Address This field is used to store the 128B (Two Cache 0000000h Line) address of main memory for which an error (single bit or multi-bit error) has occurred. Note that
  • Intel 925 | Data Sheet - Page 60
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.18 DERRSYN-DRAM Error Syndrome (D0:F0) (Intel® 82925X Only) PCI Device: Address Offset: Default Value: Access: Size: 0 5Ch 00h RO/S by software, will escape recording. These bits are reset on PWROK. 60 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 61
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.19 DERRDST-DRAM Error Destination (D0:F0) (Intel® 82925X Only) PCI Device: Address Offset: 5:0 RO/S Error Source Code: This field is updated concurrently with DERRSYN. 00h 00h = Processor to memory reads 01h-07h = Reserved 08h-09h = DMI
  • Intel 925 | Data Sheet - Page 62
    range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cache ability of these areas is controlled via the MTRR registers in the P6 processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to both host accesses and PCI
  • Intel 925 | Data Sheet - Page 63
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0C0000-0C3FFF Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 64
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0C8000h-0CBFFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 65
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0D0000h-0D3FFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 66
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0D8000h-0DBFFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 67
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0E0000h-0E3FFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 68
    DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. 3:2 Reserved 1:0 R/W 0E8000h-0EBFFFh Attribute (LOENABLE): This field controls the steering of read 00b and write cycles that address the BIOS
  • Intel 925 | Data Sheet - Page 69
    0b register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should Express Graphics Attach. 1 1 All VGA references are routed to PCI Express Graphics Attach. MDA references are routed to the DMI Intel®
  • Intel 925 | Data Sheet - Page 70
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.28 TOLUD-Top of Low Usable DRAM (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 9Ch 08h R/W 8 bits This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory are within the DRAM space defined.
  • Intel 925 | Data Sheet - Page 71
    9Dh 00h R/W/L, RO 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the supports only the SMM space between A0000h and BFFFFh, this field is
  • Intel 925 | Data Sheet - Page 72
    controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory bit is set when the processor has 0b accessed the defined memory ranges in Extended SMRAM (High Memory and T- segment) while not Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 73
    Bridge/DRAM Controller Registers (D0 Memory Flag (LCKF): 1 = MCH detected a lock operation to memory space that did not map into DRAM. Received Refresh Timeout Flag(RRTOF): 1 = 1024 memory core fields are locked to further single bit error updates until the processor clears this bit by writing a 1.
  • Intel 925 | Data Sheet - Page 74
    to non-DRAM Memory (LCKERR) 0b 1 = The MCH will generate a DMI SERR special cycle whenever a processor lock cycle is detected controller. 0 = Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC, this bit must be disabled. 82925XE MCH Reserved 74 Intel
  • Intel 925 | Data Sheet - Page 75
    (DSESMI): 1 = The MCH generates an SMI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of this condition via SMI messaging is disabled. For systems that do not support ECC, this bit must be disabled. 82925XE MCH Reserved Intel® 82925X/82925XE MCH Datasheet 75
  • Intel 925 | Data Sheet - Page 76
    controller. 0 = Reporting of this condition via SCI messaging is disabled. For systems not supporting ECC controller detects a single bit error. 0 = Reporting of this condition via SCI messaging is disabled. For systems that do not support of BIOS and graphics drivers. Bit Access & Default Description
  • Intel 925 | Data Sheet - Page 77
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.36 CAPID0-Capability Identifier (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. § Intel® 82925X/82925XE MCH Datasheet 77
  • Intel 925 | Data Sheet - Page 78
    Host Bridge/DRAM Controller Registers (D0:F0) R 78 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 79
    Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 00h - 0000h - 900122h Access R/W R/W R/W R/W - R/W R/W - R/W - R/W - R/W - R/W, RO - R/W R/W R/W R/W - R/W R/W - R/W - R/W - R/W, RO Intel® 82925X/82925XE MCH Datasheet 79
  • Intel 925 | Data Sheet - Page 80
    F10-F13h F14h Register Symbol - C1DRC0 - PMCFG PMSTS Register Name Reserved Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power Management Status Default Value - 00000000h - 00000000h the top address in that rank is 32 MB. 80 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 81
    that rank of either channel is 64 MB. Programming guide: C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB to a 1 in the highest DRB (DRB3) if 4 GB of memory is present. Intel® 82925X/82925XE MCH Datasheet 81
  • Intel 925 | Data Sheet - Page 82
    Range: Address Offset: Default Value: Access: Size: MCHBAR 103h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. 82 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 83
    MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 109h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRA0. Intel® 82925X/82925XE MCH Datasheet 83
  • Intel 925 | Data Sheet - Page 84
    00h R/W 8 bits This register can be used to disable the system memory clock signals to each DIMM slot. This can significantly reduce EMI and Affected SCLK_A[2:0]/ SCLK_A[2:0]# SCLK_A[5:3]/ SCLK_A[5:3]# SCLK_B[2:0]/ SCLK_B[2:0]# SCLK_B[5:3]/ SCLK_B[5:3]# 84 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 85
    . 01 = 8 Bank. 1X = Reserved 3:2 R/W Rank 1 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved 1:0 R/W Rank 0 Bank Architecture 00b 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved Description Intel® 82925X/82925XE MCH Datasheet 85
  • Intel 925 | Data Sheet - Page 86
    set to overlap with time period that requires a refresh to happen. The DRAM controller includes a separate tRAS-MAX counter for every supported bank. With a maximum of four ranks, and four banks per rank, there CL 00 5 01 4 10 3 11 Reserved Reserved 86 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 87
    6:4 R/W DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted 010b between a row activate command and - 111 = Reserved 3 Reserved 2:0 R/W DRAM RAS Precharge (tRP). This bit controls the number of clocks that are 010b inserted between a row precharge command and an
  • Intel 925 | Data Sheet - Page 88
    for communication of software state between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Reserved Refresh Mode . Refresh interval 64 clocks (fast refresh mode) Other = Reserved Reserved 88 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 89
    the DRAM interface. 011 = Mode Register Set Enable - All processor cycles to DRAM result in a "mode register" set command on supported SDRAM types. This bit is controlled by the MTYPE strap signal. 00 = Reserved 01 = Reserved 10 = Second Revision Dual Data Rate (DDR2) SDRAM 11 = Reserved Intel
  • Intel 925 | Data Sheet - Page 90
    Range: Address Offset: Default Value: Access: Size: MCHBAR 188h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRA0. 90 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 91
    Size: MCHBAR 194h 900122h R/W 32 bits The operation of this register is detailed in the description for register C0DRT1. C1DRC0-Channel B DRAM Controller Mode 0 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 1A0h 00000000h R/W 32 bits The operation of this register is detailed
  • Intel 925 | Data Sheet - Page 92
    BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit sequence. 0 = Channel A not guaranteed to be in self-refresh. 1 = Channel A in Self-Refresh. § 92 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 93
    Declaration Topology MCH X16 PEG (Port #2) Link #2 (Type 1) Link #1 (Type 0) Egress Port (Port #0) DMI (Port #1) Link #2 (Type 0) Link #1 (Type 0) Main Memory Subsystem Link #1 (Type 0) X4 Egress Port (Port #0) Intel® ICH6 Egress_LinkDeclar_Topo Intel® 82925X/82925XE MCH Datasheet 93
  • Intel 925 | Data Sheet - Page 94
    . Number of Link Entries: This field indicates the number of link entries following the Element Self Description. This field reports 2 (one each for PCI Express* x16 Graphics Interface and DMI). Reserved Element Type: This field Indicates the type of the Root Complex Element. 1h = Port to system
  • Intel 925 | Data Sheet - Page 95
    it is mirrored. Reserved Link Type: This bit indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of Reserved Link Address: This field provides the memory-mapped base address of the RCRB that is the target element (DMI) for this
  • Intel 925 | Data Sheet - Page 96
    associated with the element targeted by this link entry (PCI Express* x16 Graphics Interface). The target port number is with respect to the 1 = Link points to configuration space of the integrated device that controls the x16 root port. The link address specifies the configuration address (
  • Intel 925 | Data Sheet - Page 97
    19:15 14:12 11:0 Access & Default RO 00h RO 0 0001b RO 000b Description Reserved Bus Number Device Number: Target for this link is PCI Express* x16 port (Device 1). Function Number Reserved § Intel® 82925X/82925XE MCH Datasheet 97
  • Intel 925 | Data Sheet - Page 98
    EPBAR Registers-Egress Port Register Summary R 98 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 99
    Registers-Direct Media Interface (DMI) RCRB R 7 DMIBAR Registers-Direct Media Interface (DMI) RCRB This Root Complex Register Block (RCRB) controls the MCH-Intel ICH6 serial interconnect. The base address of this space is programmed in DMIBAR in device 0 configuration space. These registers are
  • Intel 925 | Data Sheet - Page 100
    : This field indicates the next item in the list. Capability Version: This field indicates support as a version 1 capability structure. Capability ID: This field indicates this is the Virtual additional VC (VC1) that exists with extended capabilities. 100 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 101
    the root complex. VC1 is highest priority and VC0 is lowest priority. DMIPVCCTL-DMI Port VC Control MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 00Ch 00000000h R/W, RO 16 bits defined as read/write with always returning 0 on reads. Intel® 82925X/82925XE MCH Datasheet 101
  • Intel 925 | Data Sheet - Page 102
    , not 0b just advanced packet switching transactions. Reserved RO Port Arbitration Capability (PAC): This field indicates that this VC uses fixed 01h port arbitration. 102 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 103
    Offset: Default Value: Access: Size: DMIBAR 014h 8000007Fh R/W, RO 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit 31 30:27 26:24 23:20 19:17 16 15:8 7:1 class is mapped to the virtual channel. Reserved Intel® 82925X/82925XE MCH Datasheet 103
  • Intel 925 | Data Sheet - Page 104
    3h indicates the table is at offset 30h. Reserved RO Maximum Time Slots (MTS): This value is updated by platform BIOS based upon 00h the determination of the number of time slots available in the platform 01h capability is time-based WRR of 128 phases. 104 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 105
    : Address Offset: Default Value: Access: Size: DMIBAR 020h 00100000h R/W, RO 32 bits This register controls the resources associated with Virtual Channel 1. Bit 31 30:27 26:24 23:20 19:17 16 this transaction class is mapped to the virtual channel. Reserved Intel® 82925X/82925XE MCH Datasheet 105
  • Intel 925 | Data Sheet - Page 106
    This bit is cleared after the table has been updated. 7.1.11 DMILCAP-DMI Link Capabilities MMIO Range: Reserved L1 Exit Latency (EL1). L1 not supported on DMI. L0s Exit Latency (EL0): This field . Active State Link PM Support (APMS): This field indicates that L0s is supported on DMI. Maximum Link
  • Intel 925 | Data Sheet - Page 107
    TS1 sequences at exit from L1 prior to entering L0. 6:2 Reserved 1:0 R/W Active State Link PM Control (APMC): Indicates whether DMI should enter L0s. 00b 00 = Disabled 01 = L0s entry enabled 10 reserved. RO Link Speed (LS) 1h Link is 2.5 Gb/s. § Intel® 82925X/82925XE MCH Datasheet 107
  • Intel 925 | Data Sheet - Page 108
    DMIBAR Registers-Direct Media Interface (DMI) RCRB R 108 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 109
    Express* Graphics Bridge Registers (D1:F0) Device 1contains the controls associated with the PCI Express x16 root port that is the intended to attach as the point for external graphics. It is typically referred to as PCI Express* x16 Graphics RO - RO RO R/W Intel® 82925X/82925XE MCH Datasheet 109
  • Intel 925 | Data Sheet - Page 110
    Signaled Interrupts Capability ID Message Control Message Address Message Data Reserved PCI Express* Capability List PCI Express Capabilities Device Capabilities Device Control Device Status Link Capabilities Link Control Link Status Slot Capabilities Slot Control Default Value - F0h 00h 00h
  • Intel 925 | Data Sheet - Page 111
    PEGSSTS - Register Name Slot Status Root Control Reserved Root Status Reserved PCI Express*-Graphics Legacy Control Reserved Virtual Channel Enhanced Capability Header Port VC RO R/W - RO RO, R/W - RO RO RO, R/W - RO - RO RO, R/WO - RO, R/WO - R/WO - RO - Intel® 82925X/82925XE MCH Datasheet 111
  • Intel 925 | Data Sheet - Page 112
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1 8.1.1 8.1.2 Device 1 Configuration Register Details VID1-Vendor Identification (D1:F0) PCI identifier assigned to the 2581h MCH device 1 (virtual PCI-to-PCI bridge, PCI Express* Graphics port). 112 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 113
    by sending an SERR message to the Intel® ICH6. This bit, when set, enables reporting of non-fatal and fatal errors to the Root Complex. Note that errors are reported if enabled either through this bit or through the PCI Express* specific bits in the Device Control Register 0 = The SERR message is
  • Intel 925 | Data Sheet - Page 114
    Express* Graphics Bridge Registers (D1:F0) R 8.1.4 Bit Access & Default Description 2 R/W Bus Master Enable (BME): This bit does not affect forwarding of completions 0b from the primary interface to the secondary interface. 0 = This device is prevented from making memory not supported on
  • Intel 925 | Data Sheet - Page 115
    8 RO Master Data Parity Error (PMDPE): Because the primary side of the PCI 0b Express* x16 Graphics Interface's virtual PCI-to-PCI bridge is integrated with the MCH functionality, there is no , PCICMD1[10], has no effect on this bit. 2:0 Reserved Intel® 82925X/82925XE MCH Datasheet 115
  • Intel 925 | Data Sheet - Page 116
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.5 RID1-Revision Identification (D1:F0) PCI as the RID values in all other devices in this component. See Intel® 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register. 8.1.6 CC1-Class Code
  • Intel 925 | Data Sheet - Page 117
    -PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.7 8.1.8 8.1.9 CL1-Cache Line Size (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 0Ch 00h R/W 8 bits Bit Access & Default Description 7:0 R/W Cache Line Size (Scratch pad): This field is implemented by PCI Express
  • Intel 925 | Data Sheet - Page 118
    bridge i.e. to PCI Express Graphics. This number is programmed by the cycles to PCI Express Graphics. Bit Access & at the level below PCI Express Graphics. This number is programmed by the configuration cycles to PCI Express Graphics. Bit Access & Express*-G segment, this register will contain the same
  • Intel 925 | Data Sheet - Page 119
    Value: Access: Size: 1 1Ch F0h RO 8 bits This register controls the processor-to-PCI Express Graphics I/O access routing based on the following formula: IO_BASE ≤ address be passed to the PCI Express* hierarchy associated with this device. 3:0 Reserved Intel® 82925X/82925XE MCH Datasheet 119
  • Intel 925 | Data Sheet - Page 120
    Express* Graphics conditions associated with secondary side (i.e., PCI Express Graphics side) of the "virtual" PCI-PCI the SERR Enable bit in the Bridge Control register is 1. 13 R/WC Received set when the Parity Error Enable bit in the Bridge Control register is set. 7 RO Fast Back-to-Back
  • Intel 925 | Data Sheet - Page 121
    R/W 16 bits This register controls the processor to PCI Express Graphics non-prefetchable memory access routing based on the Memory Address Base (MBASE): This field corresponds to A[31:20] of the FFFh lower limit of the memory range that will be passed to PCI Express*. 3:0 Reserved Intel
  • Intel 925 | Data Sheet - Page 122
    controls the processor-to-PCI Express Graphics non-prefetchable memory Express Graphics address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller covered with the main memory). There is no provision 15:4 R/W Memory Address Limit (MLIMIT): This
  • Intel 925 | Data Sheet - Page 123
    RO, R/W 16 bits This register, in conjunction with the corresponding Upper Base Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits
  • Intel 925 | Data Sheet - Page 124
    , controls the processor-to-PCI Express Graphics prefetchable memory access memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 125
    -PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.20 INTRLINE1-Interrupt Line (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 3Ch 00h R/W 8 bits This register contains interrupt line routing information. The device itself does not use this value; rather device drivers and
  • Intel 925 | Data Sheet - Page 126
    Express* Graphics Bridge Registers (D1:F0) R 8.1.22 BCTRL1-Bridge Control control for the secondary interface (i.e., PCI Express Host-PCI Express bridge embedded corresponding PCI Express* Port. controls the routing of processor-initiated 0b transactions targeting VGA compatible I/O and memory
  • Intel 925 | Data Sheet - Page 127
    IOLIMIT for processor I/O transactions will be mapped to PCI Express Graphics. 1 = MCH will not forward to PCI Express Graphics any I/O enabled by the Root Control register. 0 RO Parity Error Response Enable (PEREN): This bit controls whether or not the Intel® 82925X/82925XE MCH Datasheet 127
  • Intel 925 | Data Sheet - Page 128
    Express* Graphics Support: This field indicates the power states in which this device may indicate PME wake via PCI Express driver is to use it. Auxiliary Power Source (APS): Hardwired to 0. PME Clock: Hardwired to 0 to indicate this device does NOT support list is the PCI Express* capability at A0h.
  • Intel 925 | Data Sheet - Page 129
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.24 PM_CS1-Power Management Control/Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 84h 00000000h RO, R/W/S 32 bits Bit 31:16 15 14:13 12:9 8 7:2 1:0 Access & Default
  • Intel 925 | Data Sheet - Page 130
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.25 SS_CAPID-Subsystem ID and Vendor ID Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access and is the same as the vendor ID that is assigned by the PCI Special Interest Group. 130 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 131
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.27 MSI_CAPID-Message Signaled Interrupts Capability ID (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 90h A005h RO 16 bits When a device supports MSI, it can generate an interrupt request to the processor by writing a
  • Intel 925 | Data Sheet - Page 132
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.28 MC-Message Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 92h 0000h RO, R/W 16 bits System software can modify bits in this register, but the
  • Intel 925 | Data Sheet - Page 133
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.29 MA-Message Address (D1:F0) PCI Device: Address Offset: device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. This register supplies
  • Intel 925 | Data Sheet - Page 134
    Express* Graphics Bridge Registers (D1:F0) R 8.1.31 PEG_CAPL-PCI Express* Capability List (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 A0h 0010h RO 16 bits This register enumerates the PCI Express Express Express registers. 8.1.32 PEG_CAP-PCI Express PCI Express device
  • Intel 925 | Data Sheet - Page 135
    : Default Value: Access: Size: 1 A4h 00000000h RO 32 bits This register indicates PCI Express link capabilities. Bit Access & Default Description 31:6 Reserved 5 RO Extended Tag Field Supported: Hardwired to indicate support for 5-bit Tags as a 0b Requestor. 4:3 RO Phantom Functions
  • Intel 925 | Data Sheet - Page 136
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.34 DCTL-Device Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 A8h 0000h R/W 16 bits This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in
  • Intel 925 | Data Sheet - Page 137
    Express* Graphics Bridge Registers (D1:F0) R 8.1.35 DSTS-Device Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 AAh 0000h RO 16 bits This register reflects status corresponding to controls in the Device Control Error reporting. Intel® 82925X/82925XE MCH Datasheet 137
  • Intel 925 | Data Sheet - Page 138
    indicates the PCI Express* port number for the given PCI Express link. This it accordingly. Note: When PCI Express* is operating with separate reference Support: L0s and L1 entry supported. Max Link Width: Hardwired to indicate X16. When Force X1 mode is enabled on this PCI Express* x16 Graphics
  • Intel 925 | Data Sheet - Page 139
    to 0 to indicate 64 byte. 0b 2 Reserved 1:0 R/W Active State PM: This field controls the level of active state power management 00b supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported Intel® 82925X/82925XE MCH Datasheet 139
  • Intel 925 | Data Sheet - Page 140
    Express* Graphics Bridge Registers (D1:F0) R 8.1.38 LSTS-Link Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B2h 1001h RO 16 bits This register indicates PCI Express link 1h 1h = 2.5 Gb/s All other encodings are reserved. 140 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 141
    Express* Graphics Bridge Registers (D1:F0) R 8.1.39 SLOTCAP-Slot Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B4h 00000000h R/WO 32 bits PCI Express slot-related registers allow for the support hot-plug operations. Intel® 82925X/82925XE MCH Datasheet 141
  • Intel 925 | Data Sheet - Page 142
    Express* Graphics Bridge Registers (D1:F0) R 8.1.40 SLOTCTL-Slot Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B8h 01C0h R/W 16 bits PCI Express slot related registers allow for the support an attention button pressed event. 142 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 143
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.41 SLOTSTS-Slot Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 BAh 0X00h RO, R/W/C 16 bits PCI Express slot-related registers allow for the support of Hot-Plug. Bit Access & Default Description 15:7
  • Intel 925 | Data Sheet - Page 144
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.42 RCTL-Root Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 BCh 0000h R/W 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register
  • Intel 925 | Data Sheet - Page 145
    Express* Graphics Bridge Registers (D1:F0) R 8.1.43 RSTS-Root Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 C0h 00000000h RO, R/W/C 32 bits This register provides information about PCI Express again and updating the Requestor Intel® 82925X/82925XE MCH Datasheet 145
  • Intel 925 | Data Sheet - Page 146
    = Enable. Generate a GPE PME message when PME is received (Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables the MCH to support PMEs on the PCI Express* x16 Graphics Interface port under legacy OSs. 1 R/W Hot-Plug GPE Enable (HPGPE) 0b 0 = Do not generate GPE Hot-Plug message when
  • Intel 925 | Data Sheet - Page 147
    Express* Graphics Bridge Registers (D1:F0) R 8.1.45 VCECH-Virtual Channel Enhanced Capability Header (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 100h 14010002h RO 32 bits This register indicates PCI Express supported by the device. Intel® 82925X/82925XE MCH Datasheet 147
  • Intel 925 | Data Sheet - Page 148
    Express* Graphics Bridge Registers (D1:F0) R 8.1.47 PVCCAP2-Port VC Capability Register 2 (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 108h 00000001h RO 32 bits This register describes the configuration of PCI Express Port VC Control (D1: Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 149
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.49 Value: Access: Size: 1 114h 8000007Fh RO, R/W 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit 31 30:27 26:24 23:8 7:1 0 Access routed to VC0. Intel® 82925X/82925XE MCH Datasheet 149
  • Intel 925 | Data Sheet - Page 150
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.51 VC0RSTS (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the Request. Reserved 150 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 151
    Express* Graphics Bridge Registers (D1:F0) R 8.1.53 VC1RCTL-VC1 Resource Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 120h 01000000h RO, R/W 32 bits Controls the resources associated with PCI Express is always routed to VC0. Intel® 82925X/82925XE MCH Datasheet 151
  • Intel 925 | Data Sheet - Page 152
    the status of the process of Flow Control initialization. It is set by default element (PCI Express* x16 Graphics Interface) to other Express Link Declaration Capability. Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link Declaration Topology. 152 Intel
  • Intel 925 | Data Sheet - Page 153
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.56 ESD-Element Self Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: ). Reserved Element Type: This field indicates the type of the Root Complex Element. 0h = root port. Intel® 82925X/82925XE MCH Datasheet 153
  • Intel 925 | Data Sheet - Page 154
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.57 LE1D-Link Entry 1 Description (D1: everywhere that it is mirrored. Reserved Link Type: This field indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target
  • Intel 925 | Data Sheet - Page 155
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.58 LE1A-Link & Default R/WO 0 0000h Description Reserved Link Address: This field indicates memory-mapped base address of the RCRB that is the target element (Egress Port) acknowledged TLP. § Intel® 82925X/82925XE MCH Datasheet 155
  • Intel 925 | Data Sheet - Page 156
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 156 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 157
    FSB pins are decoded to determine whether the access is above or below 4 GB. The MCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express 64-bit prefetchable memory transactions, or any other addressing mechanism that allows addressing of greater than 4 GB on either the DMI or
  • Intel 925 | Data Sheet - Page 158
    so that adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated. • In the case of overlapping ranges with memory, the memory decode will be given priority. • There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges
  • Intel 925 | Data Sheet - Page 159
    memory controlled by the MCH. Legacy Video Area (A_0000h-B_FFFFh) The legacy 128-KB VGA memory range, frame buffer, (000A_0000h - 000B_FFFFh) can be mapped to PCI Express internally mapped devices, namely the PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI depends on the
  • Intel 925 | Data Sheet - Page 160
    support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to PCI Express (000B_0000h - 000B_7FFFh) and forward either PCI Express or the DMI. In addition to the memory range B0000h to B7FFFh, the MCH decodes I/O
  • Intel 925 | Data Sheet - Page 161
    , the MCH can "shadow" BIOS into main memory. When disabled, this segment is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory. Table 9-3. System BIOS Area Memory Segments Memory Segments 0F0000h-0FFFFFh Attributes WE RE Comments BIOS Area
  • Intel 925 | Data Sheet - Page 162
    Express memory space. This means that as the amount of physical memory populated in the system reaches 4 GB, there will be physical memory that exists, yet nonaddressable; therefore, this memory memory disabled by opening the hole is not remapped to the top of the memory; that physical main memory
  • Intel 925 | Data Sheet - Page 163
    Graphics VGA memory. 9.3 PCI Memory Address Range (TOLUD - 4 GB) This address range, from the top of physical memory to 4 GB (top of addressable memory space supported by the MCH) is normally mapped via the DMI to PCI. Note: AGIP Aperture no longer exists with PCI Express. Intel® 82925X
  • Intel 925 | Data Sheet - Page 164
    Programmable windows, graphics ranges, PCI Express* Port chipset, but may also exist as stand-alone components. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor
  • Intel 925 | Data Sheet - Page 165
    the FSB. Any device on PCI Express or DMI may issue a memory write to 0FEEx_xxxxh. The MCH will forward this memory write along with the data to the MB, but the minimum processor MTRR range for this region is 2 MB; thus, that full 2 MB must be considered. PCI Express* Configuration Address Space A
  • Intel 925 | Data Sheet - Page 166
    PCI Express* Graphics Attach The MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within either of two programmed ranges specified via registers in the MCH's Device 1 configuration space. • The first range is controlled via the Memory Base Register
  • Intel 925 | Data Sheet - Page 167
    processor has immediate access to this memory space upon entry to SMM. MCH provides three SMRAM options: • Below 1-MB option that supports to properly execute above 1 MB. Note: DMI and PCI Express masters are not allowed to access the SMM space. 9.4.1 SMM Intel® 82925X/82925XE MCH Datasheet 167
  • Intel 925 | Data Sheet - Page 168
    main memory, or to any "PCI" devices (including DMI, PCI Express, and graphics devices Processor originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA capability is enabled; otherwise, they are forwarded to the DMI. PCI Express Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 169
    forwarded to the DMI or PCI Express. The SMM software can use this bit to write to video memory while running SMM code out of DRAM. Table 9-6. SMM Control Table G_SMRAME D_LCK 0 x 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 D_CLS X X 0 0 1 1 X 0 1 D_OPEN x 0 0 1 0 1 x x x CPU in SMM Mode
  • Intel 925 | Data Sheet - Page 170
    to BIOS. PCI Express and DMI write accesses through the graphics memory range set up by Express and DMI read accesses to the graphics memory range set up by BIOS are not supported not specific to PCI Express or DMI; it applies to the processor. Also, since the graphics memory range snoop would not
  • Intel 925 | Data Sheet - Page 171
    been done on previous chipsets. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into 2 transactions by the processor. PCI Express* I/O Address Mapping The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when
  • Intel 925 | Data Sheet - Page 172
    System Address Map R 172 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 173
    This chapter describes the MCH interfaces and major functional units. Host Interface The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. The cache line size is 64 bytes prior to being driven on the bus. When the processor or Intel® 82925X/82925XE MCH Datasheet 173
  • Intel 925 | Data Sheet - Page 174
    Memory Controller This section describes the MCH system memory interface for DDR2 memory. The MCH supports DDR2 memory and either one or two DIMMs per channel. Memory Organization Modes The system memory controller supports two styles of memory clarification. 174 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 175
    Functional Description R Figure 10-1. System Memory Styles Single Channel Dual Channel Interleaved (channels do not have to match) Dual Channel Asymmetric (channels do not have to match) CL CL TOM CH B TOM CH A CH A 2560 MB 2560 MB 2304 MB 1792 MB Intel® 82925X/82925XE MCH Datasheet 175
  • Intel 925 | Data Sheet - Page 176
    the MCH control the system memory operation. Following the MCH is configured in a dual interleaved mode, each register represents When the MCH is configured in a dual-channel lock-step or interleaved mode, registers of each DIMM in the channel. • DRAM Control (CxDRCy): The x represents a channel, A (
  • Intel 925 | Data Sheet - Page 177
    . • The DRAM sub-system supports single or dual channels, 64b wide per channel Dual Channel Asymmetric mode, any DIMM slot may be populated in any order. • In Dual Channel Interleaved mode, any DIMM slot may be populated in any order, but the total memory in each channel must be the same. Intel
  • Intel 925 | Data Sheet - Page 178
    -5 specify the host interface to memory interface address multiplex for the MCH. Refer to the details of the various DIMM configurations as described in Table 10-3. The address lines specified in the column header refer to the host (processor) address lines. 178 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 179
    Functional Description R Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) Tech Banks Page Size Rank Size 31 30 29 28 27 26 25 24 c4 c3 c2 c1 c0 NOTES: 1. b - 'bank' select bit 2. c - 'column' address bit 3. r - 'row' address bit Intel® 82925X/82925XE MCH Datasheet 179
  • Intel 925 | Data Sheet - Page 180
    Functional Description R Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode) Tech Banks Page Size Rank Size 31 30 29 28 27 26 c0 NOTES: 1. b - 'bank' select bit 2. c - 'column' address bit 3. h - channel select bit 4. r - 'row' address bit 180 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 181
    supported DIMM. There are a total of 6 clock pairs driven directly by the MCH to 2 DIMMs per channel. Suspend to RAM and Resume When entering the Suspend-to-RAM (STR) state, the SDRAM controller of on the motherboard. The MCH drives out the required ODT signals, based on memory configuration and
  • Intel 925 | Data Sheet - Page 182
    processor/memory subsystem to a PCI Express hierarchy. The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model (a load-store architecture with a flat address space) is maintained to ensure that all existing applications and drivers manages flow control of TLPs
  • Intel 925 | Data Sheet - Page 183
    1.0b support • ACPI S0, S3, S4, S5, C0, C1, C2, C3, C4 • Enhanced power management state transitions for increasing time the processor spends in low power states • Graphics Adapter States: D0, D3. • PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3 • PM_THRMTRIP# output • Conditional memory Self
  • Intel 925 | Data Sheet - Page 184
    Pair ITP Processor Processor Diff Pair Processor Diff Pair Processor Diff Pair PCIExpress GFX PCI Express Diff Pair x16 PCI Exp PCI Express Diff LPC GlueChip Port80 PCI SATA PLL PCI Express PLL USB PLL Intel® ICH6 OSC 24 MHzBit Cl o ck 32.768 KHz High Def Audio 1 4 .0 0 0 M Hz §
  • Intel 925 | Data Sheet - Page 185
    Tstorage MCH Core Storage Temperature -55 150 °C 1 VCC 1.5 V Core Supply Voltage Memory Supply Voltage with -0.3 4.0 V Respect to VSS VCCA_SMPLL 1.5 V System Memory PLL Analog Supply Voltage -0.3 1.65 V (DDR2) with respect to VSS PCI Express* / DMI Interface VCC_EXP 1.5 V PCI Express
  • Intel 925 | Data Sheet - Page 186
    Table 11-2. Non-Memory Power Characteristics Symbol Parameter Signal Names Min Typ IVTT 1.2 V System Bus Supply VTT Bus Current - - IVCC 1.5 V Core Supply Current VCC (Integrated) - - IVCC 1.5 V Core Supply Current VCC (Discrete) - - IVCC_EXP 1.5 V PCI Express* and DMI Supply
  • Intel 925 | Data Sheet - Page 187
    * Interface Signal Groups (e) PCI Express* Input PCI Express Interface: EXP_RXN(15:0), EXP_RXP(15:0), (f) PCI Express Output PCI Express Interface: EXP_TXN(15:0), EXP_TXP(15:0) (g) Analog EXP_COMP0 PCI Express I/F EXP_COMPI Compensation Signals Intel® 82925X/82925XE MCH Datasheet 187
  • Intel 925 | Data Sheet - Page 188
    (q) 1.2 V System Bus Input VTT Supply Voltage (r) 1.5 V PCI Express Supply Voltages VCC_EXP (t) 1.8 V DDR2 Supply Voltage VCCSM (DDR2) (v) DDR2 PLL Analog VCCA_SMPLL (DDR2) Supply Voltage (w) 1.5 V MCH Core Supply VCC Voltage (x) 2.5 V CMOS Supply Voltage VCC2 (z) PLL
  • Intel 925 | Data Sheet - Page 189
    Voltage VCC_EXP (r) PCI Express* Supply 1.425 1.5 Voltage VTT (q) System Bus Input Supply 1.09 1.2 Voltage VCC (w) MCH Core Supply Voltage 1.425 1.5 - Leakage Current - VTTmax / mA (1-0.25)Rttmin - 20 µA Rttmin = 54 Ω VOL < Vpad < VTT Intel® 82925X/82925XE MCH Datasheet 189
  • Intel 925 | Data Sheet - Page 190
    (k, l) DDR2 Input/Output Pin Capacitance 1.5 V PCI Express Interface Specification 1.0a VTX-DIFF P-P VTX_CM-ACp ZTX- 6.0 pF - 0.600 V 2 - 20 mV 100 120 Ohms - 0.600 V 3 - 150 mV - - - - 0 0.710 0.8 V - V ±10 µA 6.0 pF - V 0.850 V Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 191
    compliance test load as shown in Transmitter compliance eye diagram of the PCI Express Interface Specification 1.0a and measured over any 250 consecutive TX Uls. 3. compliance eye diagram of the PCI Express Interface Specification 1.0a should be used as the RX device when taking measurements
  • Intel 925 | Data Sheet - Page 192
    Electrical Characteristics R 192 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 193
    that are listed as RSV are reserved. Board traces should be routed to these balls. Note: Balls that are listed as NC are No Connects. Intel® 82925X/82925XE MCH Datasheet 193
  • Intel 925 | Data Sheet - Page 194
    Ballout and Package Information R Figure 12-1. Intel® 82925X/82925XE MCH Ballout (Top View: Left Side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A /SDQS_A8#/SDQS_B8/SDQS_B8# are on the 82925X MCH only. These balls are Reserved on the 82925XE MCH. 194 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 195
    Ballout and Package Information R Figure 12-2. Intel® 82925X/82925XE MCH Ballout (Top View: Right Side) 19 20 21 22 23 24 25 26 27 28 29 30 [7:0] and SDQS_A8/SDQS_A8#/SDQS_B8/SDQS_B8# are on the 82925X MCH only. These balls are Reserved on the 82925XE MCH. Intel® 82925X/82925XE MCH Datasheet 195
  • Intel 925 | Data Sheet - Page 196
    H1 K16 B11 A11 H29 K29 J29 G30 G32 K30 L29 M30 L31 L28 J28 K27 K33 M28 R29 L26 N26 M26 N31 P26 N29 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 197
    F26 F19 C29 E33 H26 J19 B29 P33 L34 N35 L33 E31 B23 F33 E32 H31 G31 F31 K34 P34 J32 D24 A23 N34 A24 Intel® 82925X/82925XE MCH Datasheet 197
  • Intel 925 | Data Sheet - Page 198
    G16 J13 K13 K15 M16 R35 D13 E13 F13 AB33 AD32 D12 AE16 AH15 AL15 AK15 AN27 AR27 AR20 AR16 AN16 AN9 AP29 AP18 198 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 199
    AH3 AJ2 AE2 AE1 AG3 AH2 AK2 AK3 AN4 AP4 AJ1 AJ3 AP2 AP3 AP5 AK7 AM9 AL7 AR5 AN5 AM7 AM8 AE17 AF16 AL17 Intel® 82925X/82925XE MCH Datasheet 199
  • Intel 925 | Data Sheet - Page 200
    AE29 AC28 AB27 AA28 W29 V28 V29 Y26 AA29 W26 U26 AG1 AG2 AL3 AL2 AP7 AN7 AH16 AG17 AK27 AJ28 AG35 AG33 AA34 200 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 201
    AR12 AP11 AP15 AP10 AN10 AM34 AJ12 AF9 AK12 AE10 AF5 AE5 AP30 AP32 AN29 AN32 AN34 AL34 AL35 AL33 AP27 AN17 AG4 AG8 AE7 Intel® 82925X/82925XE MCH Datasheet Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SVREF1 SWE_A# SWE_B# VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel 925 | Data Sheet - Page 202
    W9 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 A13 A12 B13 A14 A17 B17 AK35 AL12 AM10 AM11 AM13 AM14 AM16 AM17 202 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 203
    D28 D3 D30 D31 D32 D4 D6 D7 D8 D9 E1 E10 E17 K6 K9 L11 L13 L15 L16 L17 L18 L2 L20 L21 L22 Intel® 82925X/82925XE MCH Datasheet 203
  • Intel 925 | Data Sheet - Page 204
    F18 F2 F23 F25 F29 F30 F32 F35 F4 F5 F6 F8 G10 G11 G13 G15 G17 G19 G2 G20 G23 G26 G27 G28 204 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 205
    AR13 AR17 AR21 AR25 AR3 AR30 AR6 B10 B12 B14 B16 H13 H2 H21 H24 H25 H27 H30 H32 H34 H4 H5 H6 H9 J10 Intel® 82925X/82925XE MCH Datasheet 205
  • Intel 925 | Data Sheet - Page 206
    VTT VTT VTT VTT VTT VTT VTT VTT VTT Ball # D19 D20 D21 D22 E19 E20 E21 E22 F20 F21 F22 G21 G22 H22 206 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 207
    VSS B19 VTT B20 VTT B21 VTT B22 VTT B23 HRCOMP B24 VSS B25 HD63 B26 HDINV3# B27 HD54 B28 VSS B29 HDSTBP3# B30 HD51 Intel® 82925X/82925XE MCH Datasheet Table 12-2. MCH Ballout Sorted By Ball Number Ball # Signal Name B31 HD52 B32 HD15 B33 HD13 B34 HD11 B35 NC
  • Intel 925 | Data Sheet - Page 208
    VSS F11 EXP_RXN0 F12 NC F13 RSV F14 RSV F15 RSV F16 VSS F17 HD47 F18 VSS F19 HDSTBN2# F20 VTT F21 VTT F22 VTT Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 209
    VSS H7 EXP_RXN7 H8 EXP_RXP7 H9 VSS H10 VSS H11 EXP_RXN1 H12 NC H13 VSS H14 RSV H15 NC H16 BSEL0 H17 NC H18 HD46 Intel® 82925X/82925XE MCH Datasheet Table 12-2. MCH Ballout Sorted By Ball Number Ball # Signal Name H19 HD41 H20 HD40 H21 VSS H22 VTT H23 HD37
  • Intel 925 | Data Sheet - Page 210
    HLOCK# L34 HHIT# L35 HDBSY# M1 EXP_TXP13 M2 VSS M3 EXP_TXN12 M4 VSS M5 VSS M6 VSS M7 EXP_RXN12 M8 EXP_RXP12 M9 VSS M10 VSS Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 211
    # N30 VSS N31 HA21# N32 VSS N33 HA26# N34 HTRDY# N35 HHITM# P1 EXP_TXP15 P2 VSS P3 EXP_TXN14 P4 VSS P5 VSS P6 VSS Intel® 82925X/82925XE MCH Datasheet Table 12-2. MCH Ballout Sorted By Ball Number Ball # Signal Name P7 EXP_RXP14 P8 EXP_RXN14 P9 VSS P10 EXP_RXP11 P11 VSS
  • Intel 925 | Data Sheet - Page 212
    U20 VCC U21 VSS U22 VCC U23 VSS U24 VCC U25 VSS U26 SDQ_B63 U27 VSS U28 HA29# U29 VSS U30 SDQS_A8# (82925X) RSV (82925XE) Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 213
    VSS SDQ_A61 SDQ_A51 SDQ_A60 VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP EXP_COMPO VSS NC VCC VCC VCC VCC VCC VSS VCC VCC VCC Intel® 82925X/82925XE MCH Datasheet 213
  • Intel 925 | Data Sheet - Page 214
    VSS SDQ_B51 SDQ_B55 VSS SCB_A7 (82925X) RSV (82925XE) VSS SDQS_B6 VSS RSV SCLK_A5# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 215
    SDQ_A29 SDQ_B24 VSS VSS NC VSS SDQ_B37 SDM_B6 VSS VSS SDQ_A35 SCLK_B5 SCLK_B5# NC SDQ_A48 RSV - VSS SDQ_A49 SDQ_A5 SDQ_A4 SDQ_A0 VSS SOCOMP1 VSS SVREF0 Intel® 82925X/82925XE MCH Datasheet Table 12-2. MCH Ballout Sorted By Ball Number Ball # Signal Name AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16
  • Intel 925 | Data Sheet - Page 216
    # SDM_B0 VSS SDM_B2 SDQS_B2 VSS RSV_TP1 SDQS_A3 SDQ_A27 VSS SDQ_B30 VSS SDQ_B31 VSS SCLK_B0 NC SDQS_B4 VSS SDQ_A34 SDQS_B5 VSS SDQS_B5# SDM_B5 VSS VSS SDQ_A40 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 217
    SDQ_A44 VCCSM SDM_A1 SDQS_A1# SDQS_A1 SDQ_B9 SDQS_B1# SDQ_B14 SDQ_A19 SDQ_B10 SCLK_B1# VSS SCLK_B4# VCCSM VSS SDQ_B23 RSV_TP2 VSS SDQ_A26 SDQ_B26 VSS SCB_B4 (82925X) RSV (82925XE) Intel® 82925X/82925XE MCH Datasheet 217
  • Intel 925 | Data Sheet - Page 218
    SMA_A5 SMA_A8 - SMA_A2 SMA_A0 SBS_A0 SWE_A# SODT_A2 SMA_A13 SCS_A1# SODT_A3 SCS_B2# SODT_B0 VCCSM NC SDQ_A14 SDQ_A15 SDQ_A11 SDQ_A16 SDM_A2 SDQS_A2 VCCSM SCKE_B1 SMA_B11 SMA_B9 VCCSM Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 219
    ball pitch varies from 31.8 mils to 43.0 mils, depending on the X-axis or Y-axis direction. Figure 12-3 shows the physical dimensions of the package. Intel® 82925X/82925XE MCH Datasheet 219
  • Intel 925 | Data Sheet - Page 220
    Ballout and Package Information R Figure 12-3. MCH Package Dimensions MCH 220 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 221
    XOR 4 SM XOR 4 SM XOR 4 SM XOR 4 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 SM XOR 5 Intel® 82925X/82925XE MCH Datasheet 221
  • Intel 925 | Data Sheet - Page 222
    chain files are golden, if there is a pin missing from the chain files and exclusion list, it should be added to the exclusion list. 222 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 223
    K21 K19 H18 J19 F19 G18 K22 M21 J21 H20 H19 J24 J22 H23 A25 A29 D27 B26 B29 C29 C25 B30 E27 C30 E25 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name ICH_SYNC# EXTTS# HCPURST# HD44 HD42 HD43 HD47 HD38 HD39 HDINV2# HD46 HDSTBP2# HDSTBN2# HD45 HD34 HD36 HD35 HD40
  • Intel 925 | Data Sheet - Page 224
    HD30 HDINV1# HD26 HD29 HD15 HD7 HD1 HD4 HD2 HA6# HA3# HA13# HA5# HA15# HREQ4# HA4# HA11# HA14# HA10# HREQ0# HBPRI# HDEFER# HEDRDY# BSEL2 224 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 225
    C31 B31 D29 E28 G29 B34 B33 C32 C33 C34 D34 D33 E34 E33 E35 F34 G34 G35 J33 G32 H31 K30 J31 G31 E31 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name HD57 HD61 HD54 HD63 HD62 HD59 HD49 HD56 HD53 HD50 HD52 HD18 HD16 HD20 HD11 HD13 HD14 HD9
  • Intel 925 | Data Sheet - Page 226
    # HDBSY# HHITM# HRS1# HTRDY# HBREQ0# HA21# HA26# HA28# HREQ1# HA27# HA20# HA19# HA24# HA29# HADSTB1# HA18# HA16# HA31# HA25# HA23# HA30# HA22# HA17# RSV_M16 226 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 227
    V34 V33 U33 W33 U34 V30 AA31 AA30 Y30 AB29 V31 V32 R31 R30 AA34 W34 Y35 Y33 AD35 AE35 AE34 AA33 AA32 AD31 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQ_A58 SDQ_A59 SDQ_A63 SDQ_A60 SDQ_A62 SDQ_A56 SDQ_A57 SDM_A7 SDQ_A61 SDQS_A7 SDQS_A8 (82925X) RSV (82925XE) SCB_A2 (82925X) RSV
  • Intel 925 | Data Sheet - Page 228
    AJ28 F15 R Signal Name SCLK_A2# SCLK_A5# SCLK_A5 SDQ_A47 SDQ_A41 SDQ_A45 SDM_A5 SDQ_A43 SDQ_A42 SDQ_A46 SDQ_A40 SDQ_A44 SDQS_A5 SCS_A0# SODT_A3 SODT_A2 SODT_A1 SODT_A0 SDQS_A4# RSV_F15 228 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 229
    W27 AB31 AB27 AE31 AC26 AE27 AE29 AF27 AB26 AC28 AD24 AN33 AD29 AE25 AE26 AP34 AP33 AM33 AL33 AL34 AL35 AN34 AF30 AK32 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQ_B62 SDQ_B63 SDQ_B58 SDQ_B59 SDQ_B57 SDM_B7 SDQ_B61 SDQ_B56 SDQ_B60 SDQS_B7 SDQS_B6 SDQ_B55 SDQ_B52 SDQ_B50 SDQ_B49
  • Intel 925 | Data Sheet - Page 230
    AJ25 AL25 AJ26 AL26 AF23 AG24 C15 R Signal Name SDM_B5 SDQ_B45 SDQ_B41 SDQ_B47 SDQ_B44 SDQ_B42 SDQS_B5 SMA_B13 SDQ_B39 SDQ_B38 SDQ_B35 SDQ_B34 SDQ_B36 SDQ_B33 MTYPE 230 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 231
    AJ33 AK31 AF28 AH27 AG27 AL31 AK29 AP29 AN28 AR28 AR27 AP27 AN27 AM30 AL29 AL28 AK28 AN25 AP26 AN26 AN30 AP25 AP23 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQS_A7# SDQS_A8# (82925X) RSV (82925XE) SDQS_A6# SCLK_A2 SDQS_A5# SCS_A1# SCS_A3# SDQS_A4 SDQ_A35 SDQ_A36 SDM_A4 SDQ_A33
  • Intel 925 | Data Sheet - Page 232
    AD17 AN18 AN7 AN3 AL2 AG2 A16 R Signal Name SMA_A3 SMA_A6 SMA_A8 SDQS_A3 SDQ_A27 SDQ_A26 SDQ_A25 SDQ_A24 SDQ_A29 SCKE_A2 SDQS_A2# SCLK_A1# SDQS_A1# SDQS_A0# RSV_A16 232 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 233
    AD23 AF24 AG26 AF20 AH19 AD15 AD18 AE20 AK19 AH21 AL18 AF15 AE19 AK22 AG23 AH23 AL21 AK18 AJ23 AB29 AJ24 AL20 AJ20 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQS_B7# SDQS_B6# SCLK_B5 SDQ_B46 SDQS_B5# SDM_B4 SDQ_B37 SDQ_B32 SDQS_B4# SDQS_B3# SDQ_B30 SDQ_B29 SDQ_B24 SDM_B3 SDQ_B27
  • Intel 925 | Data Sheet - Page 234
    (82925X) RSV (82925XE) SDQS_B8# (82925X) RSV (82925XE) SRAS_B# SCAS_B# SWE_B# SBS_B0 SBS_B1 SMA_B2 SMA_B0 SMA_B10 SMA_B1 SMA_B3 SMA_B4 SCKE_B0 SDQS_B2# SCLK_B1# SDQS_B1# SDQS_B0# RSV_B15 234 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 235
    AN22 AR20 AN21 AN20 AP19 AR19 AP7 AM9 AL7 AM8 AM7 AP6 AK7 AP5 AN5 AR5 AM2 AM3 AN2 AP4 AP3 AP2 AN4 AK3 AK2 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQS_A3# SDM_A3 SDQ_A31 SDQ_A30 SDQ_A28 SCKE_A1 SMA_A11 SMA_A9 SMA_A5 SBS_A2 SMA_A7 SMA_A12 SCKE_A0 SCKE_A3 SDQS_A2 SDQ_A18 SDQ_A19
  • Intel 925 | Data Sheet - Page 236
    AH3 AJ2 AF3 AE3 AE2 AE1 C14 R Signal Name SDQ_A13 SDQ_A12 SDM_A1 SDQS_A1 SDQS_A0 SDQ_A6 SDM_A0 SDQ_A7 SDQ_A2 SDQ_A3 SDQ_A1 SDQ_A0 SDQ_A4 SDQ_A5 RSV_C14 236 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 237
    AN10 AP10 AN9 AN11 AR8 AP9 AN8 AE14 AF14 AK13 AH12 AD14 AL14 AD12 AF13 AE13 AH13 AL11 AJ11 AK9 AL4 AJ5 AH4 AK10 AL8 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name SDQS_B4 SDQS_B3 SCLK_B3 SDQS_B8 (82925X) RSV (82925XE) SMA_B6 SMA_B9 SMA_B8 SMA_B7 SMA_B12 SMA_B11 SBS_B2 SMA_B5 SCKE_B2
  • Intel 925 | Data Sheet - Page 238
    AJ6 AJ8 AH10 AG11 AH7 K15 R Signal Name SDQ_B15 SDQ_B14 SDM_B1 SDQ_B11 SDQS_B1 SDQS_B0 SDQ_B4 SDQ_B5 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B6 SDM_B0 SDQ_B0 SDQ_B7 RSV_K15 238 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 239
    B4 C5 E5 D2 G5 F3 H7 G1 J5 H3 K7 J1 L5 K3 R10 L1 M7 M3 N5 N1 P8 P3 R5 R1 E11 Intel® 82925X/82925XE MCH Datasheet Testability Signal Name EXP_RXN0 EXP_TXN0 EXP_RXN1 EXP_TXN1 EXP_RXN2 EXP_TXN2 EXP_RXN3 EXP_TXN3 EXP_RXN4 EXP_TXN4 EXP_RXN5 EXP_TXN5 EXP_RXN6 EXP_TXN6 EXP_RXN7 EXP_TXN7 EXP_RXN8 EXP_TXN8
  • Intel 925 | Data Sheet - Page 240
    EXP_TXP4 EXP_RXP5 EXP_TXP5 EXP_RXP6 EXP_TXP6 EXP_RXP7 EXP_TXP7 EXP_RXP8 EXP_TXP8 EXP_RXP9 EXP_TXP9 EXP_RXP10 EXP_TXP10 EXP_RXP11 EXP_TXP11 EXP_RXP12 EXP_TXP12 EXP_RXP13 EXP_TXP13 EXP_RXP14 EXP_TXP14 EXP_RXP15 EXP_TXP15 BSEL1 240 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 241
    U10 V10 W5 V5 H16 Testability Signal Name DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 BSEL0 Intel® 82925X/82925XE MCH Datasheet 241
  • Intel 925 | Data Sheet - Page 242
    Testability R 13.5 Pads Excluded from XOR Mode(s) A large number of pads do not support XOR testing. The majority of the pads that fall into this category are analog related DREFCLKN DREFCLKP BLUE BLUE# GREEN GREEN# RED RED# RSTIN# HSYNC VSYNC REFSET 242 Intel® 82925X/82925XE MCH Datasheet
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R
Intel
®
925X/925XE Express
Chipset
Datasheet
For the Intel
®
82925X/82925XE Memory Controller Hub (MCH)
November 2004
Document Number:
301464-003