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Intel 925 Data Sheet

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Manual

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  • Intel 925 | Data Sheet - Page 1
    R Intel® 925X/925XE Express Chipset Datasheet For the Intel® 82925X/82925XE Memory Controller Hub (MCH) November 2004 Document Number: 301464-003
  • Intel 925 | Data Sheet - Page 2
    ... Technology logo and also including an Intel® 925, 915, or 910 Express Chipset (see the product spec sheet or ask your salesperson). Performance and ... a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel EM64T. Processor...
  • Intel 925 | Data Sheet - Page 3
    ... Host Interface...16 1.3.2 System Memory Interface...17 1.3.3 Direct Media Interface (DMI)...18 1.3.4 PCI Express* Graphics Interface ...Primary PCI and Downstream Configuration Mechanism ...39 3.3.4 PCI Express* Enhanced Configuration Mechanism ...40 3.3.5 Intel® 82925X/925XE MCH Configuration Cycle ...
  • Intel 925 | Data Sheet - Page 4
    ... Address (D0:F0)...55 PCIEXBAR-PCI Express* Register Range Base Address (D0:F0...(D0:F0) ...68 LAC-Legacy Access Control (D0:F0) ...69 TOLUD-Top ...F0) ...70 SMRAM-System Management RAM Control (D0:F0)...71 ESMRAMC-Extended ... ...86 5.1.10 C0DRC0-Channel A DRAM Controller Mode 0 ...88 5.1.11 C1DRB0-Channel ...
  • Intel 925 | Data Sheet - Page 5
    ...5.1.20 5.1.21 5.1.22 6 6.1 C1DRC0-Channel B DRAM Controller Mode 0 ...91 PMCFG-Power Management Configuration... Capability ...102 7.1.6 DMIVC0RCTL0-DMI VC0 Resource Control ...103 7.1.7 DMIVC0RSTS-DMI VC0 Resource ... Interface (DMI) RCRB ...99 7.1 8 Host-PCI Express* Graphics Bridge Registers (D1:F0)...
  • Intel 925 | Data Sheet - Page 6
    ...Data (D1:F0) ...133 PEG_CAPL-PCI Express* Capability List (D1:F0) ...134 PEG_CAP-PCI Express*-G Capabilities (D1:F0)...134 DCAP-Device Capabilities (D1:...D1:F0)...145 PEGLC-PCI Express*-G Legacy Control ...146 VCECH-Virtual Channel ... (D1:F0)...155 PEGSSTS-PCI Express*-G Sequence Status (D1:F0)...155...
  • Intel 925 | Data Sheet - Page 7
    ...FSB Interrupt Memory Space (FEE0_0000h-FEEF_FFFFh) ...165 9.3.4 High BIOS Area ...165 9.3.5 PCI Express* ... TLB...170 9.4.8 Memory Shadowing ...170 9.4.9 I/O Address Space...170 9.4.10 PCI Express* I/O Address Mapping ... 10.3.5 DDR2 Off-Chip Driver Impedance Calibration...181 PCI Express* ...182 10.4.1 ...
  • Intel 925 | Data Sheet - Page 8
    R 13 Testability ...221 13.1 13.2 13.3 13.4 13.5 Complimentary Pins ...221 XOR Test Mode Initialization...222 XOR Chain Definition ...222 XOR Chains...222 Pads Excluded from XOR Mode(s) ...242 8 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 9
    R Figures Figure 1-1. Intel® 925X/925XE Express Chipset System Block Diagram Example...14 Figure 2-1. Intel® 82925X/82925XE MCH Signal Interface Diagram...22 Figure 3-1. Conceptual Intel® 925X/925XE Express Chipset Platform PCI Configuration Diagram...37 Figure 3-2. DMI Type 0 ...
  • Intel 925 | Data Sheet - Page 10
    ...31 Table 2-2. System Memory Reset and S3 States...32 Table 2-3. PCI Express* Graphics x16 Port Reset and S3 ...Address Map Summary ...99 Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1...9-5. SMM Space Table ...168 Table 9-6. SMM Control Table...169 Table 10-1. Sample System...
  • Intel 925 | Data Sheet - Page 11
    R Revision History Revision -001 -002 -003 • Initial Release • Added Intel Extended Memory 64 Technology (Intel EM64T) Support Information ® ® Description Date June 2004 August 2004 November 2004 • Added 82925XE MCH Product Information § Intel® 82925X/82925XE MCH Datasheet 11
  • Intel 925 | Data Sheet - Page 12
    ...Interface ƒ System Memory ⎯ One Intel® Pentium® 4 processor (supports ⎯ One or two 64-bit wide DDR2 SDRAM 775-land ... CKE ⎯ Supports a Cache Line Size of 64 bytes ⎯ Supports configurations defined in the ⎯ Supports Intel Pentium® 4 processors with ® Φ JEDEC DDR2 DIMM specification only...
  • Intel 925 | Data Sheet - Page 13
    ... great workstation application flexibility, the Intel® 925X/925XE Express chipset is specifically designed to support Intel® Extended Memory 64 Technology Φ... EM64T) enabling 64-bit memory addressability. Select versions of the Pentium 4 processor support Intel EM64T) as an...
  • Intel 925 | Data Sheet - Page 14
    Introduction R Figure 1-1. Intel® 925X/925XE Express Chipset System Block Diagram Example Intel® Pentium® 4 Processor 200/266 MHz FSB (800/1066 MT/s) Intel® 925X/925XE Express Chipset System Memory DDR2 Channel A Display Graphics Card PCI Express x16 Graphics...
  • Intel 925 | Data Sheet - Page 15
    ... Terminology Term Core DBI DDR2 DMI FSB Full Reset Host INTx Intel ICH6 ® Description Core refers to the internal base ...MCH and the Intel ICH6. Front Side Bus. The FSB is synonymous with Host or processor bus ...interface and DRAM controller. It may also contain an x16 PCI Express port (typically ...
  • Intel 925 | Data Sheet - Page 16
    Introduction R 1.2 Reference Documents Document Title Intel 925X/925XE Express Chipset Thermal Design Guide Intel I/O Controller Hub 6 ...DDR2 SDRAM. The MCH also supports the new PCI Express based external graphics attach. Thus, the 925X/925XE Express chipset is not compatible with AGP (1X, 2X, 4X, ...
  • Intel 925 | Data Sheet - Page 17
    ...(DDR2) memory is supported; consequently, the buffers support only SSTL_1.8 V signal interfaces. The memory controller interface is fully configurable through a .... • I/O Voltage of 1.9 V for DDR2 533 MHz CL3-3-3. • Supports non-ECC and ECC (925X only) memory. • Supports 256-Mb, 512-Mb and 1-Gb ...
  • Intel 925 | Data Sheet - Page 18
    ... direction) • 100 MHz reference clock (shared with PCI Express Graphics Attach). • 32-bit downstream addressing • APIC and MSI interrupt messaging support. Will send Intel-defined "End Of Interrupt" broadcast message when initiated by the processor. • Message Signaled ...
  • Intel 925 | Data Sheet - Page 19
    ...(asynchronous snooped, PCI ordering) • Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-relaxed ordering) ...4 processor FSB interrupt delivery mechanisms. • Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI ⎯ MSIs routed directly to FSB ...
  • Intel 925 | Data Sheet - Page 20
    ... This includes 2X and 4X for internal optimizations. The PCI Express core clock of 250 MHz is generated from a separate PCI Express PLL. This clock uses the fixed 100 MHz Serial ... as defined in the Clock Generator specification. Host, Memory, and PCI Express* x16 Graphics PLLs, and ...
  • Intel 925 | Data Sheet - Page 21
    ... for complete details. The MCH integrates GTL+ termination resistors, and supports VTT of from 0.83 V to 1.65 V (including guardbanding). PCI-Express interface signals. These signals are compatible with PCI Express 1.0 Signaling Environment AC ...
  • Intel 925 | Data Sheet - Page 22
    ...SDQS_B[8:0]# SCKE_B[3:0] SCLK_B[5:0], SCLK_B[5:0]# SODT_B[3:0] PCI Express x16 Graphics Port EXP_RXN[15:0],...RSTIN# PWROK EXTTS# BSEL[2:0] MTYPE ICH_SYNC# Processor System Bus Interface Clocks, Reset,...VCC2 VCCA_EXPPLL VCCA_HPLL VCCA_SMPLL VSS System Memory DDR2 Ref./ Comp. SRCOMP[1:0] SOCOMP[1:0]...
  • Intel 925 | Data Sheet - Page 23
    ...GTL+ HBPRI# O GTL+ Description Address Strobe: The processor bus owner asserts HADS# to indicate ... Request: The MCH is the only Priority Agent on the processor bus. It asserts this signal to obtain the ownership ... in a known state. Note that the Intel ICH6 must provide processor frequency select strap...
  • Intel 925 | Data Sheet - Page 24
    ...[31:3]# during snoop cycles on behalf of DMI and PCI Express Graphics initiators. HA[31:3]# are transferred at 2x rate. ...the negation of HLOCK# must be atomic (i.e., no DMI or PCI Express Graphics accesses to DRAM are allowed when HLOCK# is asserted by the processor). Precharge Request: The processor...
  • Intel 925 | Data Sheet - Page 25
    ... carry additional information to define the complete transaction type. The transactions supported by the MCH Host Bridge are defined in the Host Interface section of... GTL+ Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. ...
  • Intel 925 | Data Sheet - Page 26
    ...complement SCLK_Ax# are used to sample the command and control signals on the SDRAM. SDRAM Complementary Differential ... chip select for each SDRAM rank. Memory Address: These signals are used to provide ... require a 6-layer board to be routed. SCB_A[7:0] ® (Intel 82925X Only) SDQS_A[8:0] (82925X MCH)...
  • Intel 925 | Data Sheet - Page 27
    ...complement SCLK_Bx# are used to sample the command and control signals on the SDRAM. SDRAM Complementary Differential ...one chip select for each SDRAM rank Memory Address: These signals are used to provide... require a 6-layer board to be routed. SCB_B[7:0] ® (Intel 82925X Only) SDQS_B[8:0] (82925X MCH...
  • Intel 925 | Data Sheet - Page 28
    ... O PCIE I A EXP_COMPI I A EXP_SLR I CMOS PCI Express Graphics Output Current Compensation Note:... numbers are reversed. For example, the MCH PCI Express interface signals can be configured as follows... EXP_TXP15 EXP_TXP14 ...EXP_TXP1...EXP_TXP0 PCI Express Graphics Transmit Differential Pair Description...
  • Intel 925 | Data Sheet - Page 29
    .... This clock is used to generate the clocks necessary for the support of PCI Express. Display PLL Differential Clock In DREFCLKN ... signal will asynchronously reset the MCH ® logic. This signal is connected to the PLTRST# output of the Intel ICH6. All PCI Express Graphics Attach output signals will ...
  • Intel 925 | Data Sheet - Page 30
    Signal Description R 2.8 Power and Ground Name VCC VTT VCC_EXP VCCSM Voltage 1.5 V 1.2 V 1.5 V 1.8 V Core Power. Processor System Bus Power. PCI Express* and DMI Power. System Memory Power. DDR2: VCCSM = 1.8 V (VCCSM = 1.9 V for DDR2 ...
  • Intel 925 | Data Sheet - Page 31
    Signal Description R Table 2-1. Host Interface Reset and S3 States Interface Signal Name I/O State During RSTIN# Assertion DRIVE LV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM HV TERM ...
  • Intel 925 | Data Sheet - Page 32
    Signal Description R Table 2-2. System Memory Reset and S3 States Interface Signal Name...S3 Pull-up/ Pull-down System Memory Channel A SCLK_A[5:0] SCLK_A[5:0]# SCS_A[3:0]# SMA_A[...LV SDQS_A[8:0] SDQS_A[8:0]# SCKE_A[3:0] SODT_A[3:0] System Memory Channel B SCLK_B[5:0] SCLK_B[5:0]# SCS_B[3:0]# SMA_B[...
  • Intel 925 | Data Sheet - Page 33
    .... 2. SDQS_A8/SDQS_A8# and SDQS_B8/SDQS_B8# are on the 82925X MCH only. Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States Interface Signal Name I/O ... RCOMP) TRI (after RCOMP) S3 Pull-up/ Pull-down PCI Express*Graphics EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15:0] EXP_TXP[15:0] EXP_COMPO ...
  • Intel 925 | Data Sheet - Page 34
    Signal Description R Table 2-5. Clocking Reset and S3 States Interface Signal Name HCLKN HCLKP GCLKN GCLKP DREFCLKN DREFCLKP I/O I I I I I I State During RSTIN# Assertion IN IN IN IN IN IN State After RSTIN# Deassertion IN IN IN IN IN IN S3 Pull-up/ Pull-down Clocks IN IN IN IN IN IN Table 2-6....
  • Intel 925 | Data Sheet - Page 35
    .... • Control registers are I/O mapped into the processor I/O space that control access to PCI and PCI Express configuration space (see ... registers (I/O Mapped, Configuration and PCI Express Extended Configuration registers) are accessible by the processor. The registers that reside within the lower ...
  • Intel 925 | Data Sheet - Page 36
    ...Host Bridge entity that are marked either "Reserved" or "Intel Reserved". The MCH responds to accesses to "Reserved"...have no effect on the MCH. Registers that are marked as "Intel Reserved" must not be modified by system... may cause system failure. Reads from "Intel Reserved" registers may return a non...
  • Intel 925 | Data Sheet - Page 37
    ... PCI Bus 0 to configuration software. This is shown in Figure 3-1. Figure 3-1. Conceptual Intel® 925X/925XE Express Chipset Platform PCI Configuration Diagram Processor Intel® 82925X/82925XE MCH PCI Configuration Window in I/O Space DRAM ...
  • Intel 925 | Data Sheet - Page 38
    ... for routing configuration cycles to the proper interface. Configuration cycles to the Intel ICH6 internal devices and Primary PCI (including downstream devices) are routed to the Intel ICH6 via DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility ...
  • Intel 925 | Data Sheet - Page 39
    ... Bus 0. The Host-PCI Express Bridge entity within the MCH is hardwired as Device 1 on PCI Bus 0. The Intel ICH6 decodes the Type 0 access and generates a configuration ... if the configuration cycle is meant for ICH6 PCI Express ports one of the Intel ICH6's devices, the DMI, or a ...
  • Intel 925 | Data Sheet - Page 40
    ...appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express memory mapped configuration address space are not supported. All changes made ... are equivalent. The enhanced PCI Express configuration access mechanism uses a flat memory-mapped address space to...
  • Intel 925 | Data Sheet - Page 41
    Register Description R Figure 3-4. Memory Map to PCI Express* Device Configuration Space 0xFFFFFFFh ... on the FSB, but non-posted on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes). See the PCI Express Specification for more information on both the PCI ...
  • Intel 925 | Data Sheet - Page 42
    Register Description R 3.3.5 Intel® 82925X/925XE MCH Configuration Cycle Flowchart Figure 3-5. Intel® 82925X/...0 Yes No MCH Generates Type 1 Access to PCI Express Yes Bus# > Sec Bus Bus# ≤ ... 0 Yes MCH Generates Type 0 Accessto PCI Express GMCH Generates DMI Type 0 Configuration Cycle No...
  • Intel 925 | Data Sheet - Page 43
    ... Type 0 PCI configuration cycle will be generated on PCI Express Graphics. If the Bus Number is non-...Type 1 PCI configuration cycle will be generated on PCI Express Graphics. This field is mapped to byte 8 [7:0] of the request header format during PCI Express Configuration cycles and A[23:16] during ...
  • Intel 925 | Data Sheet - Page 44
    ...bridge entity, Device Number 1 for the Host-PCI Express entity. Therefore, when the Bus Number =0 and... 6 [2:0] of the request header format during PCI Express Configuration cycles and A[10:8] during... 7 [7:2] of the request header format during PCI Express Configuration cycles and A[7:2] during the DMI...
  • Intel 925 | Data Sheet - Page 45
    ... Bridge/DRAM Controller Registers (D0:F0) R 4 Host Bridge/DRAM Controller Registers (D0:F0) The DRAM Controller registers are ... Capabilities Pointer Reserved Egress Port Base Address MCH Memory Mapped Register Range Base Address PCI Express* Register Range Base Address Root Complex Register Range ...
  • Intel 925 | Data Sheet - Page 46
    Host Bridge/DRAM Controller Registers (D0:F0) R Address Offset 52h-53h 54h-57h ... Attribute Map 5 Programmable Attribute Map 6 Legacy Access Control Reserved Top of Low Usable DRAM System Management RAM Control Extended System Management RAM Control Reserved Error Status Error Command SMI Command SCI...
  • Intel 925 | Data Sheet - Page 47
    Host Bridge/DRAM Controller Registers (D0:F0) R Address Offset 109h 10Ah-10Bh 10Ch... A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary ...B DRAM Timing Register 1 Reserved Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power ...
  • Intel 925 | Data Sheet - Page 48
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1 4.1.1 Device 0 Function 0 PCI Configuration ...Identification Number (VID): PCI standard identification for Intel. 4.1.2 DID-Device Identification (D0:F0)... (DID): This field is an identifier assigned to the MCH core/primary PCI device. 48 Intel®...
  • Intel 925 | Data Sheet - Page 49
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.3 PCICMD-PCI Command (D0... for Device 0. 0 = Disable Note: That this bit only controls SERR messaging for the Device 0. Device 1 has... reporting for error conditions occurring in that device. The control bits are used in a logical OR manner to enable...
  • Intel 925 | Data Sheet - Page 50
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.4 PCISTS-PCI Status (D0:F0) PCI Device: Address Offset: Default Value: ... 8 7 6 5 4 RO 0b RO 1b 66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0. Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration ...
  • Intel 925 | Data Sheet - Page 51
    ... Identification Number (RID): This is an 8-bit value that indicates the ® revision identification number for the MCH Device 0. See Intel 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register. 4.1.6 CC-Class Code ...
  • Intel 925 | Data Sheet - Page 52
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.7 MLT-Master Latency Timer (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 0Dh 00h RO 8 bits Device 0 in the MCH is not a PCI master. Therefore this register is not implemented. Bit Access & Default Reserved Description 7:0 ...
  • Intel 925 | Data Sheet - Page 53
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.10 SID-Subsystem Identification (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 2Eh 0000h R/W/O 16 bits This value is used to identify a particular subsystem. Bit Access & Default R/WO 0000h Description 15:0 Subsystem ID (...
  • Intel 925 | Data Sheet - Page 54
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.12 EPBAR-Egress Port Base... MMIO configuration space. There is no physical memory within this 4-KB window that can be addressed....resulting in a base address for a 4-KB block of contiguous memory address space. This register ensures that a naturally ...
  • Intel 925 | Data Sheet - Page 55
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.13 MCHBAR-MCH Memory Mapped ...44h 00000000h R/W 32 bits This is the base address for the MCH memory-mapped configuration space. There is no ... base address for a 16-KB block of contiguous memory address space. This register ensures that a naturally ...
  • Intel 925 | Data Sheet - Page 56
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.14 PCIEXBAR-PCI Express* Register Range ...PCI Express BASE register. The MCH supports one PCI Express hierarchy. The 256 MB reserved by ... total addressable memory space, currently 4 GB. The address used to access the PCI Express configuration space ...
  • Intel 925 | Data Sheet - Page 57
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.15 DMIBAR-Root Complex Register Range Base Address (D0:F0)... space. This window of addresses contains the Root Complex Register set for the PCI Express hierarchy associated with the MCH. There is no physical memory within this 4-KB window that can ...
  • Intel 925 | Data Sheet - Page 58
    ...1 R/W 1b Strap dependent 0 RO 1b Reserved PCI Express* Port (D1EN): 0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb). 1 = Bus 0 Device 1 Function 0 is enabled and visible. Host Bridge:...
  • Intel 925 | Data Sheet - Page 59
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.17 DEAP-DRAM Error Address Pointer ... the 128B (Two Cache Line) address of main memory for which an error (single bit or multi-bit ... 0b Reserved Channel Indicator: This bit indicates which memory channel had the error. 0 = Channel A 1 = Channel B ...
  • Intel 925 | Data Sheet - Page 60
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.18 DERRSYN-DRAM Error Syndrome (D0:F0) (Intel® 82925X Only) PCI Device: Address Offset: Default Value: Access: Size: 0 5Ch 00h RO/S 8 bits This register is used to report the ECC syndromes for each quad word of a 32B-aligned data quantity read ...
  • Intel 925 | Data Sheet - Page 61
    ... Source Code: This field is updated concurrently with DERRSYN. 00h = Processor to memory reads 01h-07h = Reserved 08h-... cycles/data 0Eh-0Fh = Reserved 10h = PCI Express* initiated and targeting cycles/data 11h =...cycles/data 13h = Reserved 14h-16h = PCI Express* initiated and targeting cycles/data 17h ...
  • Intel 925 | Data Sheet - Page 62
    ...(PAM) Registers are used to support these features. Cache ability of these areas is controlled via the...Warning: The MCH may hang if a PCI Express graphics attach or DMI originated access ... programming of the PAM regions: At the time that a DMI or PCI Express graphics attach accesses to the PAM region ...
  • Intel 925 | Data Sheet - Page 63
    ...: Size: 0 91h 00h R/W 8 bits This register controls the read, write, and shadowing attributes ... 0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and write cycles ... writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0C0000-0C3FFF Attribute (LOENABLE): This field controls...
  • Intel 925 | Data Sheet - Page 64
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.22 PAM2-Programmable Attribute Map 2 (D0:F0)...DRAM Operation: All reads and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0C8000h-0CBFFFh Attribute (LOENABLE): This field controls the steering of read and write cycles that address the BIOS ...
  • Intel 925 | Data Sheet - Page 65
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.23 PAM3-Programmable Attribute ...00b 0D4000h-0D7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles ...and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0D0000h-0D3FFFh Attribute (LOENABLE): This field controls...
  • Intel 925 | Data Sheet - Page 66
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.24 PAM4-Programmable Attribute ...00b 0DC000h-0DFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles ...and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0D8000h-0DBFFFh Attribute (LOENABLE): This field controls...
  • Intel 925 | Data Sheet - Page 67
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.25 PAM5-Programmable Attribute ...00b 0E4000h-0E7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles ...and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0E0000h-0E3FFFh Attribute (LOENABLE): This field controls...
  • Intel 925 | Data Sheet - Page 68
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.26 PAM6-Programmable Attribute ...00b 0EC000h-0EFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles ...and writes are serviced by DRAM. 3:2 1:0 R/W 00b Reserved 0E8000h-0EBFFFh Attribute (LOENABLE): This field controls...
  • Intel 925 | Data Sheet - Page 69
    ... address range x3BCh-x3BFh are forwarded to PCI Express* if the address is within the corresponding IOBASE and ... VGA and MDA references are routed to PCI Express Graphics Attach. All VGA references are routed to PCI Express Graphics Attach. MDA references are routed to the DMI Intel® 82925X/82925XE...
  • Intel 925 | Data Sheet - Page 70
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.28 TOLUD-Top of Low Usable... address one byte above the maximum DRAM memory that is usable by the operating system. Address bits ... value to the smaller of the following 2 choices: • Maximum amount memory in the system plus one byte or the minimum ...
  • Intel 925 | Data Sheet - Page 71
    ...D0:F0) R 4.1.29 SMRAM-System Management RAM Control (D0:F0) PCI Device: Address Offset:... 9Dh 00h R/W/L, RO 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces... otherwise the access is forwarded to DMI. Since the MCH supports only the SMM space between A0000h and...
  • Intel 925 | Data Sheet - Page 72
    ... 0b Description 7 Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space location (i.e., above 1 MB or below 1 MB)... this bit becomes read only. Invalid SMRAM Access (E_SMERR): This bit is set when the processor has accessed the defined memory ranges in Extended SMRAM (High Memory and ...
  • Intel 925 | Data Sheet - Page 73
    .... Received Refresh Timeout Flag(RRTOF): 1 = 1024 memory core refreshes are enqueued. DRAM Throttle Flag... DN, and ES fields are locked until the processor clears this bit by writing a 1. Software uses ... further single bit error updates until the processor clears this bit by writing a 1. A multiple bit ...
  • Intel 925 | Data Sheet - Page 74
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.32 ERRCMD-Error Command ...SERR# signal, SERR messages are passed from the MCH to the Intel ICH6 over DMI. When a bit in this register... by the DRAM controller. 0 = Reporting of this condition via SERR messaging is disabled. For systems not supporting...
  • Intel 925 | Data Sheet - Page 75
    ... special cycle over DMI when the DRAM controller detects a single bit error. 0 = Reporting ... messaging is disabled. For systems that do not support ECC, this bit must be disabled. 82925XE... by the DRAM controller. 0 = Reporting of this condition via SMI messaging is disabled. For systems not supporting...
  • Intel 925 | Data Sheet - Page 76
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.34 SCICMD-SCI Command ... by the DRAM controller. 0 = Reporting of this condition via SCI messaging is disabled. For systems not supporting... them. It is for the convenience of BIOS and graphics drivers. Bit Access & Default R/W 00000000 h Description...
  • Intel 925 | Data Sheet - Page 77
    Host Bridge/DRAM Controller Registers (D0:F0) R 4.1.36 CAPID0-Capability Identifier (D0:F0) PCI Device: Address Offset: Default Value: Access: Size: 0 E0h 000000000001090009h RO 72 bits Bit Access & Default Reserved RO 1h RO 09h RO 00h RO 09h Description 71:28 27:24 23:16 15:8 7:0 CAPID ...
  • Intel 925 | Data Sheet - Page 78
    Host Bridge/DRAM Controller Registers (D0:F0) R 78 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 79
    ... Attribute Reserved Channel A DRAM Clock Disable Reserved Channel A DRAM Bank Architecture Reserved Channel A DRAM Timing Register Reserved Channel A DRAM Controller Mode 0 Reserved Channel B DRAM Rank Boundary Address 0 Channel B DRAM Rank Boundary Address 1 Channel B DRAM Rank Boundary Address 2 ...
  • Intel 925 | Data Sheet - Page 80
    ... - C1DRC0 - PMCFG PMSTS Reserved Register Name Default Value - 00000000h - 00000000h 00000000h Access - R/W, RO - R/W R/W/C/S Channel B DRAM Controller Mode 0 Reserved Power Management Configuration Power Management Status 5.1 5.1.1 MCHBAR Register Details C0DRB0-Channel A DRAM Rank Boundary ...
  • Intel 925 | Data Sheet - Page 81
    MCHBAR Registers R Programming guide If Channel A is empty, all of the C0DRBs are programmed with 00h. C0DRB0 = Total memory in chA rank0 (in... rank of either channel is 64 MB. Programming guide: C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 =...
  • Intel 925 | Data Sheet - Page 82
    MCHBAR Registers R 5.1.2 C0DRB1-Channel A DRAM Rank Boundary Address 1 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 101h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. 5.1.3 C0DRB2-Channel A DRAM Rank Boundary Address 2 MMIO...
  • Intel 925 | Data Sheet - Page 83
    MCHBAR Registers R 5.1.5 C0DRA0-Channel A DRAM Rank 0,1 Attribute MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 108h 00h R/W 8 bits The DRAM Rank Attribute Registers define the page sizes to be used when accessing different ranks. These registers should be left with their ...
  • Intel 925 | Data Sheet - Page 84
    ...DRAM Clock Disable MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 10Ch 00h R/W 8 bits This register can be used to disable the system memory clock signals to each DIMM slot. This can significantly reduce EMI and Power concerns for clocks that go to unpopulated DIMMs. Clocks should ...
  • Intel 925 | Data Sheet - Page 85
    MCHBAR Registers R 5.1.8 C0BNKARC-Channel A DRAM Bank Architecture MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 10Eh 0000h R/W 16 bits This register is used to program the bank architecture for each Rank. Bit Access & Default Reserved R/W 00b Rank 3 Bank Architecture 00 = 4 ...
  • Intel 925 | Data Sheet - Page 86
    ...may or may not be set to overlap with time period that requires a refresh to happen. The DRAM controller includes a separate tRAS-MAX counter for every supported bank. With a maximum of four ranks, and four banks per rank, there are 16 counters ...
  • Intel 925 | Data Sheet - Page 87
    ... R/W 010b Description 6:4 DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a read or... 3 2:0 R/W 010b Reserved DRAM RAS Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an ...
  • Intel 925 | Data Sheet - Page 88
    MCHBAR Registers R 5.1.10 C0DRC0-Channel A DRAM Controller Mode 0 MMIO Range: Address Offset: Default ... bit is used for communication of software state between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Reserved 28:11 10:8...
  • Intel 925 | Data Sheet - Page 89
    .... 011 = Mode Register Set Enable - All processor cycles to DRAM result in a "mode register" set... 110 = CBR Refresh Enable - In this mode all processor cycles to DRAM result in a CBR cycle on ...This field is used to select between supported SDRAM types. This bit is controlled by the MTYPE strap signal. ...
  • Intel 925 | Data Sheet - Page 90
    MCHBAR Registers R 5.1.11 C1DRB0-Channel B DRAM Rank Boundary Address 0 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 180h 00h R/W 8 bits The operation of this register is detailed in the description for register C0DRB0. 5.1.12 C1DRB1-Channel B DRAM Rank Boundary Address 1 ...
  • Intel 925 | Data Sheet - Page 91
    ...: Size: MCHBAR 194h 900122h R/W 32 bits The operation of this register is detailed in the description for register C0DRT1. 5.1.20 C1DRC0-Channel B DRAM Controller Mode 0 MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR 1A0h 00000000h R/W 32 bits The operation of this register is ...
  • Intel 925 | Data Sheet - Page 92
    MCHBAR Registers R 5.1.21 PMCFG-Power Management Configuration MMIO Range: Address Offset: Default Value: Access: Size: MCHBAR F10h 00000000h R/W 32 bits Bit Access & Default Reserved R/W 0b Description 31:5 4 Enhanced Power Management Features Enable 0 = Legacy power management mode 1 = ...
  • Intel 925 | Data Sheet - Page 93
    ... Register Details Figure 6-1. Link Declaration Topology MCH X16 PEG (Port #2) Link #2 (Type 1) Link #1 (Type 0) Egress Port (Port #0) Main Memory Subsystem Link #2 (Type 0) Link #1 (Type 0) DMI (Port #1) Link #1 (Type 0) X4 Intel® ICH6 Egress Port (Port #0) Egress_LinkDeclar_Topo ...
  • Intel 925 | Data Sheet - Page 94
    ... of link entries following the Element Self Description. This field reports 2 (one each for PCI Express* x16 Graphics Interface and DMI). Reserved 7:4 3:0 RO 1h Element Type: ... field Indicates the type of the Root Complex Element. 1h = Port to system memory 94 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 95
    ... 0b R/WO 0b Reserved Link Type: This bit indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base... & Default Reserved R/WO 0 0000h Link Address: This field provides the memory-mapped base address of the RCRB that is the target element (DMI) for this...
  • Intel 925 | Data Sheet - Page 96
    ... the port number associated with the element targeted by this link entry (PCI Express* x16 Graphics Interface). The target port number is with respect ... Type: 1 = Link points to configuration space of the integrated device that controls the x16 root port. The link address specifies the configuration ...
  • Intel 925 | Data Sheet - Page 97
    ... internal link to another Root Complex Element. Bit Access & Default Reserved RO 00h RO 0 0001b RO 000b Bus Number Device Number: Target for this link is PCI Express* x16 port (Device 1). Function Number Reserved Description 63:28 27:20 19:15 14:12 11:0 § Intel® 82925X/82925XE MCH Datasheet 97
  • Intel 925 | Data Sheet - Page 98
    EPBAR Registers-Egress Port Register Summary R 98 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 99
    ... This Root Complex Register Block (RCRB) controls the MCH-Intel ICH6 serial interconnect. The base address of... Port VC Capability Register 2 DMI Port VC Control Reserved DMI VC0 Resource Capability DMI VC0... DMI VC1 Resource Capability DMI VC1 Resource Control Reserved DMI VC1 Resource Status Reserved ...
  • Intel 925 | Data Sheet - Page 100
    ... 31:20 19:16 15:0 Pointer to Next Capability: This field indicates the next item in the list. Capability Version: This field indicates support as a version 1 capability structure. Capability ID: This field indicates this is the Virtual Channel capability item. 7.1.2 DMIPVCCAP1-DMI Port VC ...
  • Intel 925 | Data Sheet - Page 101
    ... field indicates that the VC arbitration is fixed in the root complex. VC1 is highest priority and VC0 is lowest priority. 7.1.4 DMIPVCCTL-DMI Port VC Control MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 00Ch 00000000h R/W, RO 16 bits Bit Access & Default Reserved R/W 000b RO ...
  • Intel 925 | Data Sheet - Page 102
    DMIBAR Registers-Direct Media Interface (DMI) RCRB R 7.1.5 DMIVC0RCAP-DMI VC0 Resource Capability MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 010h 00000001h RO 32 bits Bit Access & Default RO 00h Description 31:24 23 22:16 15 14 13:8 7:0 Port Arbitration Table Offset (AT...
  • Intel 925 | Data Sheet - Page 103
    ...-Direct Media Interface (DMI) RCRB R 7.1.6 DMIVC0RCTL0-DMI VC0 Resource Control MMIO Range: Address Offset: Default Value: Access: Size... 014h 8000007Fh R/W, RO 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access & Default RO 1b Description 31 30:...
  • Intel 925 | Data Sheet - Page 104
    DMIBAR Registers-Direct Media Interface (DMI) RCRB R 7.1.7 DMIVC0RSTS-DMI VC0 Resource Status MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 01Ah 00000002h RO 16 bits This register reports the Virtual Channel specific status. Bit Access & Default Reserved RO 1b VC Negotiation ...
  • Intel 925 | Data Sheet - Page 105
    ... Registers-Direct Media Interface (DMI) RCRB R 7.1.9 DMIVC1RCTL1-DMI VC1 Resource Control MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 020h 00100000h R/W, RO 32 bits This register controls the resources associated with Virtual Channel 1. Bit Access & Default R/W 0b ...
  • Intel 925 | Data Sheet - Page 106
    ...RO 4h RO 1h L1 Exit Latency (EL1). L1 not supported on DMI. L0s Exit Latency (EL0): This field indicates ... ns to less than 256 ns. Active State Link PM Support (APMS): This field indicates that L0s is supported on DMI. Maximum Link Width (MLW): This field indicates the maximum link width is 4 ports. ...
  • Intel 925 | Data Sheet - Page 107
    ... Interface (DMI) RCRB R 7.1.12 DMILCTL-DMI Link Control MMIO Range: Address Offset: Default Value: Access: Size: This register allows control of DMI. Bit Access & Default Reserved R/W 0h...L0. Reserved R/W 00b Active State Link PM Control (APMC): Indicates whether DMI should enter L0s...
  • Intel 925 | Data Sheet - Page 108
    DMIBAR Registers-Direct Media Interface (DMI) RCRB R 108 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 109
    ...Registers (D1:F0) Device 1contains the controls associated with the PCI Express x16 root port ... for external graphics. It is typically referred to as PCI Express* x16 Graphics Interface port. In addition...-to-PCI bridge. Warning: When reading the PCI Express "conceptual" registers such as this, you may...
  • Intel 925 | Data Sheet - Page 110
    ... Vendor ID Message Signaled Interrupts Capability ID Message Control Message Address Message Data Reserved PCI Express* Capability List PCI Express Capabilities Device Capabilities Device Control Device Status Link Capabilities Link Control Link Status Slot...
  • Intel 925 | Data Sheet - Page 111
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R Address Offset BA-BBh ... Control Reserved Root Status Reserved PCI Express*-Graphics Legacy Control Reserved Virtual Channel Enhanced ...Description Reserved Link Entry 1 Address Reserved PCI Express*-Graphics Sequence Status Reserved Intel® 82925X...
  • Intel 925 | Data Sheet - Page 112
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1 8.1.1 Device 1 Configuration Register ... Vendor Identification (VID1): PCI standard identification for Intel. 8.1.2 DID1-Device Identification (D1:F0) ... device 1 (virtual PCI-to-PCI bridge, PCI Express* Graphics port). 112 Intel® 82925X/...
  • Intel 925 | Data Sheet - Page 113
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.3 PCICMD1-PCI Command ... the SERRB condition by sending an SERR ® message to the Intel ICH6. This bit, when set, enables reporting ...through this bit or through the PCI Express* specific bits in the Device Control Register 0 = The SERR message...
  • Intel 925 | Data Sheet - Page 114
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R Bit Access & Default ... associated with primary side of the "virtual" Host-PCI Express bridge in the MCH. Bit Access & Default ...Hardwired to 0. Parity (generating poisoned TLPs) is not supported on the primary side of this device. Signaled System ...
  • Intel 925 | Data Sheet - Page 115
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R Bit Access & Default RO 0b RO 0b RO 00b RO 0b ... uses the fastest possible decode. Master Data Parity Error (PMDPE): Because the primary side of the PCI Express* x16 Graphics Interface's virtual PCI-to-PCI bridge is integrated with the MCH ...
  • Intel 925 | Data Sheet - Page 116
    ...stepped" through the manufacturing process. It is always the same as the RID values in all other devices in this ® component. See Intel 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register. 8.1.6 CC1-...
  • Intel 925 | Data Sheet - Page 117
    ... Size (Scratch pad): This field is implemented by PCI Express* devices as a read/write field for legacy ... but have no impact on any PCI Express device functionality. 8.1.8 HDR1-Header Type (D1... bits This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus 0. Bit ...
  • Intel 925 | Data Sheet - Page 118
    ... to the second bus side of the "virtual" bridge i.e. to PCI Express Graphics. This number is programmed by the PCI configuration software to allow ... the subordinate bus (if any) that resides at the level below PCI Express Graphics. This number is programmed by the PCI configuration software to allow ...
  • Intel 925 | Data Sheet - Page 119
    ...1Ch F0h RO 8 bits This register controls the processor-to-PCI Express Graphics I/O access routing ...15:12] of the I/O addresses passed by bridge 1 to PCI Express*-G. BIOS must not set this register ...: 1 1Dh 00h R/W 8 bits This register controls the processor-to-PCI Express Graphics I/O access routing...
  • Intel 925 | Data Sheet - Page 120
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.14 SSTS1-Secondary Status ...of error conditions associated with secondary side (i.e., PCI Express Graphics side) of the "virtual" PCI-PCI Bridge... set when the Parity Error Enable bit in the Bridge Control register is set. 7 6 5 4:0 RO 0b RO 0b...
  • Intel 925 | Data Sheet - Page 121
    ... Size: 1 20h FFF0h R/W 16 bits This register controls the processor to PCI Express Graphics non-prefetchable memory access routing based on ...corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. Reserved Intel® 82925X/82925XE MCH Datasheet...
  • Intel 925 | Data Sheet - Page 122
    ...: Size: 1 22h 0000h R/W 16 bits This register controls the processor-to-PCI Express Graphics non-prefetchable memory access routing based on ...-and-play manner to the prefetchable address range for improved processor-PCI Express memory access performance. Note: Configuration software ...
  • Intel 925 | Data Sheet - Page 123
    ... the corresponding Upper Base Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on the ... corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. 64-bit Address Support: This field indicates that the ...
  • Intel 925 | Data Sheet - Page 124
    ..., in conjunction with the corresponding Upper Limit Address register, controls the processor-to-PCI Express Graphics prefetchable memory access routing based on ...of the address range passed to PCI Express*. 64-bit Address Support: This field indicates the bridge supports only...
  • Intel 925 | Data Sheet - Page 125
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.20 INTRLINE1-Interrupt Line ...itself does not use this value; rather device drivers and operating systems use it to determine priority ... Interrupt Pin: As a single function device, the PCI Express* device specifies INTA as its interrupt pin. ...
  • Intel 925 | Data Sheet - Page 126
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.22 BCTRL1-Bridge Control ...bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as well as some bits ...affect the overall behavior of the "virtual" Host-PCI Express bridge embedded within MCH (e.g., VGA...
  • Intel 925 | Data Sheet - Page 127
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R Bit Access & Default R/W 0b ... addresses defined by the IOBASE and IOLIMIT for processor I/O transactions will be mapped to PCI Express Graphics. 1 = MCH will not forward to PCI Express Graphics any I/O transactions addressing the last 768 bytes...
  • Intel 925 | Data Sheet - Page 128
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.23 PM_CAPID1-Power Management Capabilities (... device may indicate PME wake via PCI Express messaging. D0, D3hot, and D3cold. This ... 1, then the next item in the capabilities list is the PCI Express* capability at A0h. Capability ID: Value of ...
  • Intel 925 | Data Sheet - Page 129
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.24 PM_CS1-Power Management Control/Status (D1:F0) PCI Device:...PME# generation from D3cold. Data Scale: This field indicates that this device does not support the power management data register. Data Select: This field indicates that ...
  • Intel 925 | Data Sheet - Page 130
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.25 SS_CAPID-Subsystem ID and Vendor ID Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 88h 0000800Dh RO 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides. ...
  • Intel 925 | Data Sheet - Page 131
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.27 MSI_CAPID-Message ..., go directly from the PCI PM capability to the PCI Express capability. Bit Access & Default RO A0h... pointer to the next item in the capabilities list that is the PCI Express* capability. Capability ID: 05h = Identifies ...
  • Intel 925 | Data Sheet - Page 132
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.28 MC-Message Control (D1:F0) PCI Device: Address Offset: Default ... of them must be serviced, the device must not generate the same message again until the driver services the earlier one. Bit Access & Default Reserved RO 0b R/W 000b 64-...
  • Intel 925 | Data Sheet - Page 133
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.29 MA-Message Address (D1:F0) PCI Device: Address Offset: ... device. When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. This ...
  • Intel 925 | Data Sheet - Page 134
    ...Registers (D1:F0) R 8.1.31 PEG_CAPL-PCI Express* Capability List (D1:F0) PCI... list item (capability structure) as being for PCI Express registers. 7:0 RO 10h 8.1.32 PEG_CAP... Number: Hardwired to 0. Slot Implemented 0 = The PCI Express* Link associated with this port is connected to an integrated...
  • Intel 925 | Data Sheet - Page 135
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.33 DCAP-Device Capabilities ... RO 32 bits This register indicates PCI Express link capabilities. Bit Access & Default Reserved... support for 5-bit Tags as a Requestor. Phantom Functions Supported: Hardwired to 0. Max Payload Size: Hardwired to...
  • Intel 925 | Data Sheet - Page 136
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.34 DCTL-Device Control (D1:F0) PCI Device: Address Offset: ... Value: Access: Size: 1 A8h 0000h R/W 16 bits This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to ...
  • Intel 925 | Data Sheet - Page 137
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.35 DSTS-Device ... whether error reporting is enabled or not in the Device Control Register. Fatal Error Detected: 1 = Fatal ...whether error reporting is enabled or not in the Device Control register. Correctable Error Detected: 1 = Correctable ...
  • Intel 925 | Data Sheet - Page 138
    ...R/WO 16 bits This register indicates PCI Express device specific capabilities. Bit Access &...BIOS must initialize it accordingly. Note: When PCI Express* is operating with separate reference clocks, L0s ...X16. When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface device, this field ...
  • Intel 925 | Data Sheet - Page 139
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.37 LCTL-Link Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B0h 0000h RO, R/W 16 bits This register allows control of PCI Express link. Bit Access & Default Reserved Reserved. Must be 0 when writing this ...
  • Intel 925 | Data Sheet - Page 140
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.38 LSTS-Link Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B2h 1001h RO 16 bits This register indicates PCI Express link status. Bit Access & Default Reserved RO 1b Slot Clock Configuration 0 = The device uses...
  • Intel 925 | Data Sheet - Page 141
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.39 SLOTCAP-Slot Capabilities (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B4h 00000000h R/WO 32 bits PCI Express slot-related registers allow for the support of Hot-Plug. Bit Access & Default R/WO 0000h Description...
  • Intel 925 | Data Sheet - Page 142
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.40 SLOTCTL-Slot Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 B8h 01C0h R/W 16 bits PCI Express slot related registers allow for the support of Hot-Plug. Bit Access & Default Reserved R/W 01b Power...
  • Intel 925 | Data Sheet - Page 143
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.41 SLOTSTS-Slot Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 BAh 0X00h RO, R/W/C 16 bits PCI Express slot-related registers allow for the support of Hot-Plug. Bit Access & Default Reserved RO Xb ...
  • Intel 925 | Data Sheet - Page 144
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.42 RCTL-Root Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 BCh 0000h R/W 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register ...
  • Intel 925 | Data Sheet - Page 145
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.43 RSTS-Root Status (D1:F0) PCI Device: Address Offset:...Access: Size: 1 C0h 00000000h RO, R/W/C 32 bits This register provides information about PCI Express Root Complex specific parameters. Bit Access & Default Reserved RO 0b PME Pending: ...
  • Intel 925 | Data Sheet - Page 146
    ...Deassert_PMEGPE messages on DMI). This enables the MCH to support PMEs on the PCI Express* x16 Graphics Interface ...received via the PCI Express* x16 Graphics Interface port from an external Intel device and will be subsequently forwarded to the ® Intel ICH6 (via Assert_GPE and Deassert_GPE messages ...
  • Intel 925 | Data Sheet - Page 147
    ... Capability Version: Hardwired to 1 to indicate compliances with the 1.0a version of the PCI Express specification. Extended Capability ID: Value of 0002 h ... RO, R/WO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & Default ...
  • Intel 925 | Data Sheet - Page 148
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.47 PVCCAP2-Port VC ... RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & ... is the lowest priority. 8.1.48 PVCCTL-Port VC Control (D1:F0) PCI Device: Address Offset: ...
  • Intel 925 | Data Sheet - Page 149
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.49 VC0RCAP-VC0 Resource Capability (D1:F0) PCI Device...Access: Size: 1 114h 8000007Fh RO, R/W 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access & Default RO 1b Description 31 30:27 26:24 ...
  • Intel 925 | Data Sheet - Page 150
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.51 VC0RSTS-VC0 Resource Status (D1:F0) ... of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual ...
  • Intel 925 | Data Sheet - Page 151
    ...-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.53 VC1RCTL-VC1 Resource Control (D1... RO, R/W 32 bits Controls the resources associated with PCI Express Virtual Channel 1. Bit ... that the VC is enabled (Flow Control Initialization is completed for the PCI Express* port); a 0 read from this bit ...
  • Intel 925 | Data Sheet - Page 152
    ...0005h Description Pointer to Next Capability: This is the last capability in the PCI Express* extended capabilities list. Link Declaration Capability Version: Hardwired to 1 to indicate compliances with the 1.0a version of the PCI Express specification. Extended Capability ID: Value of 0005h...
  • Intel 925 | Data Sheet - Page 153
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.56 ESD-Element Self Description (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 144h 02000100h RO, R/WO 32 bits This register provides information about the root complex element containing this Link Declaration ...
  • Intel 925 | Data Sheet - Page 154
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.57 LE1D-Link Entry 1 Description (D1:F0) PCI Device: ...15:2 1 0 RO 0b R/WO 0b Reserved Link Type: This field indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target ...
  • Intel 925 | Data Sheet - Page 155
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.58 LE1A-Link Entry 1...:32 31:12 11:0 8.1.59 PEGSSTS-PCI Express*-G Sequence Status (D1:F0) PCI Device: ... 218h 0000000000000FFFh RO 64 bits This register provides PCI Express status reporting that is required by the PCI Express specification...
  • Intel 925 | Data Sheet - Page 156
    Host-PCI Express* Graphics Bridge Registers (D1:F0) R 156 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 157
    .... The MCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express 64-bit prefetchable memory transactions, or any... isochronous agent and writes from the processor (4-KB window). • Device 1: Function 0: ⎯ MBASE1/MLIMIT1 - PCI Express port non-prefetchable memory...
  • Intel 925 | Data Sheet - Page 158
    ...the BIOS or system designer's responsibility to limit memory population so that adequate PCI, PCI Express, High BIOS, PCI Express Memory ... peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to PCI Express VGA range writes. Figure 9-1 shows the system memory address map in a ...
  • Intel 925 | Data Sheet - Page 159
    ... 128-KB VGA memory range, frame buffer, (000A_0000h - 000B_FFFFh) can be mapped to PCI Express and/or to the DMI. The appropriate mapping is programmable. Based ... positively decodes internally mapped devices, namely the PCI Express. Subsequent decoding of regions mapped to PCI Express or...
  • Intel 925 | Data Sheet - Page 160
    ...-000B_FFFFh. Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. PCI Express and DMI originated ... to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to PCI Express or the DMI (...
  • Intel 925 | Data Sheet - Page 161
    ...Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory. Table 9-2. Extended System ... into main memory. When disabled, this segment is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory. Table 9-3. System BIOS ...
  • Intel 925 | Data Sheet - Page 162
    ...) This address range extends from 1 MB to the top of physical memory that is permitted to be accessible by the MCH (as programmed by BIOS). All ...maximum main memory address decode space of 4 GB. The MCH does not remap APIC or PCI Express memory space. This means that as the amount of physical memory ...
  • Intel 925 | Data Sheet - Page 163
    ... DRAM at the same address. Non-processor originated accesses are not allowed to SMM space. PCI Express and DMI originated cycles to enabled SMM space are handled ... PCI. Note: AGIP Aperture no longer exists with PCI Express. Intel® 82925X/82925XE MCH Datasheet 163
  • Intel 925 | Data Sheet - Page 164
    ...DMI Interface (subtractively decode) F000_0000h PCI Express Configuration Space E000_0000h 4 GB - 512 ...) Programmable windows, graphics ranges, PCI Express* Port could be here TOLUD PCI_Address_Ranges_G-P-.... The I/O APIC(s) usually reside in the ICH6 portion of the chipset, but may also exist as stand...
  • Intel 925 | Data Sheet - Page 165
    ... SMM space to maintain cache coherency. PCI Express and DMI originated cycles to enabled SMM... FSB. Any device on PCI Express or DMI may issue a memory write to 0FEEx_xxxxh. The MCH ...devices and functions that are potentially a part of the PCI Express root complex hierarchy. This range will be aligned ...
  • Intel 925 | Data Sheet - Page 166
    ... The MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within .... The MCH positively decodes memory accesses to PCI Express memory address space as defined by.... The PCICMD1 register can override the routing of memory accesses to PCI Express. In other words,...
  • Intel 925 | Data Sheet - Page 167
    ... Management Mode uses main memory for System Management RAM (SMM RAM). The MCH supports: Compatible SMRAM (... hidden from the system OS so that the processor has immediate access to this memory space upon entry to ... above 1 MB. Note: DMI and PCI Express masters are not allowed to access the SMM space....
  • Intel 925 | Data Sheet - Page 168
    ... address space assigned to system main memory, or to any "PCI" devices (including DMI, PCI Express, and graphics devices). ...SMM space is effectively disabled. Processor originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA capability is enabled; otherwise, they are ...
  • Intel 925 | Data Sheet - Page 169
    ... to the DMI or PCI Express. The SMM software can use this bit to write to video memory while running SMM code... Decode and Transaction Handling Only the processor is allowed to access SMM space. PCI Express and DMI originated transactions are not allowed to SMM space. 9.4.6 Processor WB Transaction ...
  • Intel 925 | Data Sheet - Page 170
    ...invalid and go to address 0h. This is not specific to PCI Express or DMI; it applies to the processor. Also, since the graphics memory range snoop would not be...bus. The MCH generates either DMI or PCI Express bus cycles for all processor I/O accesses that it does not claim. Within the ...
  • Intel 925 | Data Sheet - Page 171
    ... are assumed to be split into 2 transactions by the processor. 9.4.10 PCI Express* I/O Address Mapping The MCH ... to direct non-memory (I/O) accesses to the PCI Express bus interface when processor-initiated I/O cycle ...128-KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to PCI Express (Device...
  • Intel 925 | Data Sheet - Page 172
    System Address Map R 172 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 173
    ... and major functional units. Host Interface The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. ... Bus Inversion The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the processor. DBI ...
  • Intel 925 | Data Sheet - Page 174
    ... • Flat-Logical • Clustered-Logical 10.2 System Memory Controller This section describes the MCH system memory interface for DDR2 memory. The MCH supports DDR2 memory... DIMMs per channel. 10.2.1 Memory Organization Modes The system memory controller supports two styles of memory...
  • Intel 925 | Data Sheet - Page 175
    Functional Description R Figure 10-1. System Memory Styles Dual Channel Interleaved (channels do not have to match) CL TOM CH B CH A TOM CH ... B CH A 0 Scheme XOR Bit 6 => CL Sys_Mem_Styles Single Channel Dual Channel Asymmetric (channels do not have to match) CL CL ...
  • Intel 925 | Data Sheet - Page 176
    ... registers located in the PCI configuration space of the MCH control the system memory operation. Following is a brief description of ... the SPD registers of each DIMM in the channel. • DRAM Control (CxDRCy): The x represents a channel, A (where x = 0) or B (where x = 1). A second register for a ...
  • Intel 925 | Data Sheet - Page 177
    ... modes. • The DRAM sub-system supports single or dual channels, 64b wide per ...x16 on the same DIMM) are not supported • By using 1-Gb technology, the largest memory capacity is 8 GB... are supported at 1.9 V. 10.3.1.1 Rules for Populating DIMM Slots • In all modes, the frequency of system memory...
  • Intel 925 | Data Sheet - Page 178
    ... Description R 10.3.1.2 System Memory Supported Configurations The MCH supports the 256-Mbit, 512-...Table 10-3. Table 10-3. DDR2 DIMM Supported Configurations Technology Configuration # of Row Address ... specified in the column header refer to the host (processor) address lines. 178 Intel® 82925X/...
  • Intel 925 | Data Sheet - Page 179
    Functional Description R Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) Rank Size Page Size Banks Tech 31 30 29 28 27 26 r10 25 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 24 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 23 r7 r7 r7 r7 r7 r7 r7 r7 r7 r7 22 r6 r6 r6 r6 r6 r6 r6 r6 r6 r6 21 ...
  • Intel 925 | Data Sheet - Page 180
    Functional Description R Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode) Rank Size Page Size Banks Tech 31 30 29 28 27 r10 26 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 25 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 24 r7 r7 r7 r7 r7 r7 r7 r7 r7 r7 23 r6 r6 r6 r6 r6 r6 r6 r6 r6 r6 22 r5 r5 r5 r5 ...
  • Intel 925 | Data Sheet - Page 181
    ... inside the DRAM devices themselves, instead of on the motherboard. The MCH drives out the required ODT ... resistance. 10.3.5 DDR2 Off-Chip Driver Impedance Calibration The OCD impedance adjustment ... is handled by software. The MCH adjusts the DRAM driver impedance by issuing OCD commands to the DIMM...
  • Intel 925 | Data Sheet - Page 182
    ... for further details. The MCH is part of a PCI Express root complex. This means it connects a host processor/memory subsystem to a PCI Express hierarchy. The PCI Express ...that all existing applications and drivers operate unchanged. The PCI Express configuration uses standard mechanisms ...
  • Intel 925 | Data Sheet - Page 183
    ...in low power states • Graphics Adapter States: D0, D3. • PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3... to generate memory and internal graphics core clocks. It uses the Host clock (HCLKIN) as a reference. • PCI Express PLL - This PLL generates all PCI Express related clocks, including ...
  • Intel 925 | Data Sheet - Page 184
    ... Slot 2 Diff Pair Processor Memory Main PLL SSC PCI Express GFX HPLL PCI Express Diff Pair... Express Diff Pair PCI Express Dif f Pair PCI Express Dif f Pair PCI Express... x1 PCI Exp SATA PLL P CI Express PLL CK410 48Pin SSOP 48 ... PCI 33 MHz PCI 33 MHz Intel ® ICH6 66/33 Buffer PCI ...
  • Intel 925 | Data Sheet - Page 185
    ...Respect to VSS 1.5 V System Memory PLL Analog Supply Voltage with respect to VSS -0.3 -0.3 4.0 1.65 V V PCI Express* / DMI Interface VCC_EXP VCCA_EXPPL L CMOS Interface VCC2... may occur if the MCH temperature exceeds 150 °C. Intel does not guarantee functionality for parts that have...
  • Intel 925 | Data Sheet - Page 186
    ...V Core Supply Current (Integrated) 1.5 V Core Supply Current (Discrete) 1.5 V PCI Express* and DMI Supply Current 2.5 V CMOS Supply Current 1.5 V PCI Express and DMI PLL Analog Supply Current... Estimate is only for max current coming through the chipset's supply balls. 2. Rail includes PLL current...
  • Intel 925 | Data Sheet - Page 187
    ...System Memory (1.8 V CMOS buffers)(1.9 V CMOS buffers for DDR 533 CAS timing 3-3-3) PCI Express*...Interface Signals. These signals are compatible with the PCI Express Interface Specification 1.0a signaling environment ...: EXP_RXN(15:0), EXP_RXP(15:0), PCI Express Interface: EXP_TXN(15:0), EXP_TXP(15:0)...
  • Intel 925 | Data Sheet - Page 188
    ... Supply Voltages (q) (r) (t) 1.2 V System Bus Input Supply Voltage 1.5 V PCI Express Supply Voltages 1.8 V DDR2 Supply Voltage 1.5 V DDR2 PLL Analog Supply Voltage 1.5 V MCH Core Supply Voltage 2.5 V CMOS Supply Voltage PLL Analog Supply Voltages VTT VCC_EXP VCCSM (...
  • Intel 925 | Data Sheet - Page 189
    ... (v) (r) (q) (w) (x) (z) DDR2 I/O Supply Voltage DDR2 I/O PLL Analog Supply Voltage PCI Express* Supply Voltage System Bus Input Supply Voltage MCH Core Supply Voltage CMOS Supply Voltage Various PLL's Analog Supply Voltages 1.7 1.425 1.425 ...
  • Intel 925 | Data Sheet - Page 190
    ... (k) (k, l) DDR2 Output Low Voltage DDR2 Output High Voltage Input Leakage Current DDR2 Input/Output Pin Capacitance - - - - 0.3 V V 1 1 ±10 6.0 µA pF 1.5 V PCI Express Interface Specification 1.0a VTX-DIFF P-P VTX_CM-ACp ZTX-DIFF-DC VRX-DIFF p-p VRX_CM-ACp (f) (f) (f) (e) (e) Differential...
  • Intel 925 | Data Sheet - Page 191
    ... compliance test load as shown in Transmitter compliance eye diagram of the PCI Express Interface Specification 1.0a and measured over any 250 consecutive TX ... Uls. The test load shown in Receiver compliance eye diagram of the PCI Express Interface Specification 1.0a should be used as the RX device ...
  • Intel 925 | Data Sheet - Page 192
    Electrical Characteristics R 192 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 193
    Ballout and Package Information R 12 12.1 Ballout and Package Information This chapter provides the ballout and package information. Ballout Figure 12-1 and Figure 12-2 show the 82925X/82925XE MCH ballout as viewed from the top side of the package. Table 12-1 provides the MCH ballout sorted by ...
  • Intel 925 | Data Sheet - Page 194
    Ballout and Package Information R Figure 12-1. Intel® 82925X/82925XE MCH Ballout (Top View: Left Side) 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR 2 3 4 5 VSS 6 7 8 9 10 VSS 11 GCLKP GCLKN 12 VCCA_DPLLA 13 VCC2 VCCA_DPLLB 14 VCCA_EXPPLL 15...
  • Intel 925 | Data Sheet - Page 195
    Ballout and Package Information R Figure 12-2. Intel® 82925X/82925XE MCH Ballout (Top View: Right Side) 19 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR 20 21 22 23 HSWING HRCOMP 24 HVREF 25 HD48 26 HDINV3# 27 HD54 28 VSS 29 HDSTBP3# 30 31 32 ...
  • Intel 925 | Data Sheet - Page 196
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name BSEL0 BSEL1 BSEL2 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DREFCLKN DREFCLKP EXP_COMPI EXP_COMPO ...
  • Intel 925 | Data Sheet - Page 197
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADS# HADSTB0# HADSTB1# HBNR# HBPRI# HBREQ0# HCLKN HCLKP HCPURST# HD00 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 ...
  • Intel 925 | Data Sheet - Page 198
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name ICH_SYNC# MTYPE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ball # M14 C15 A34 A35 AA12 AB12 AC23 AC24 AD21 AD30 AE18 AE30 AF19 AF22 AG25 AG29...
  • Intel 925 | Data Sheet - Page 199
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SCB_A0 (82925X) RSV (82925XE) SCB_A1 (82925X) RSV (82925XE) SCB_A2 (82925X) RSV (82925XE) SCB_A3 (82925X) RSV (82925XE) SCB_A4 (82925X) RSV (82925XE) SCB_A5 (82925X) RSV (82925XE) SCB_A6 (82925X) RSV (...
  • Intel 925 | Data Sheet - Page 200
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 ...
  • Intel 925 | Data Sheet - Page 201
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name SDQS_A6# SDQS_A7 SDQS_A7# SDQS_A8 (82925X) RSV (82925XE) SDQS_A8# (82925X) RSV (82925XE) SDQS_B0 SDQS_B0# SDQS_B1 SDQS_B1# SDQS_B2 SDQS_B2# SDQS_B3 SDQS_B3# SDQS_B4 SDQS_B4# SDQS_B5 SDQS_B5# SDQS_B6 SDQS_B6...
  • Intel 925 | Data Sheet - Page 202
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # W22 W24 Y13 Y14 AA13 AA14 AA16 AA18 AA20 AA21 ...
  • Intel 925 | Data Sheet - Page 203
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball #...
  • Intel 925 | Data Sheet - Page 204
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # L24 L27 L30 L32 L4 L7 L8 L9 M10 M11 M17 M2 M20 ...
  • Intel 925 | Data Sheet - Page 205
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # G4 G7 G8 G9 H10 N25 N28 N30 N32 N4 N7 N8 N9 P11...
  • Intel 925 | Data Sheet - Page 206
    Ballout and Package Information R Table 12-1. MCH Ballout Sorted By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # J15 J16 J17 J18 J2 J20 J23 J30 J4 J7 J8 J9 K10 ...
  • Intel 925 | Data Sheet - Page 207
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 - NC VSS - VSS EXP_TXN3 EXP_TXP3 EXP_TXN1 EXP_TXP1 VSS GCLKP VCCA_DPLLA VCC2 VCCA_EXPPLL RSV...
  • Intel 925 | Data Sheet - Page 208
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # C29 C30 C31 C32 C33 C34 C35 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Signal Name HDSTBN3# HD17 HD50 HD14 HD9 HD12 VSS - EXP_TXN5 VSS VSS EXP_RXP5 VSS VSS VSS...
  • Intel 925 | Data Sheet - Page 209
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 Signal Name VSS NC VSS HDSTBN1# HD23 HD22 VSS VSS HREQ4# VSS HREQ0# HD6 VSS EXP_TXN7 VSS...
  • Intel 925 | Data Sheet - Page 210
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 Signal Name VSS VSS HDSTBP2# VSS HD35 HD32 VSS HD33 HD27 HDINV1# HD21 HA13# HA5# VSS ...
  • Intel 925 | Data Sheet - Page 211
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 N1 N2 N3 N4 N5 N6 N7 N8 Signal Name VSS DREFCLKN DREFCLKP ICH_SYNC# RSV RSV VSS HD42 HD38 VSS HD36 HCLKN HCLKP ...
  • Intel 925 | Data Sheet - Page 212
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 Signal Name EXP_RXN15 EXP_RXP15 VSS VSS VSS EXP_RXN11 VSS NC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC NC VSS ...
  • Intel 925 | Data Sheet - Page 213
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # U31 U32 U33 U34 U35 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 Signal Name VSS VSS SDM_A7 SDQS_A7 SDQS_A7# VSS VSS Table 12-2. MCH Ballout Sorted By ...
  • Intel 925 | Data Sheet - Page 214
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Signal Name VSS VCC VCC VSS SDQ_B60 VSS SDQS_B7# VSS SCB_A6 (82925X) RSV (82925XE) Y31 Y32 Y33 Y34 Y35 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 ...
  • Intel 925 | Data Sheet - Page 215
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 Signal Name RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV...
  • Intel 925 | Data Sheet - Page 216
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG1 AG2 AG3 Signal Name VSS RSTIN# VSS SM_SLEWIN1 VSS SDQ_B5 ...
  • Intel 925 | Data Sheet - Page 217
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # AH35 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 Signal Name SDQ_A41 SDQ_A12 SDQ_A3 SDQ_A13 VSS SDQ_B13 SDQ_B3 SDQ_B2 SDQ_B6 VSS VSS SCLK_B4 SM_SLEWIN0 VSS NC VSS VSS SDQ_A31...
  • Intel 925 | Data Sheet - Page 218
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # AL21 Signal Name SCB_B6 (82925X) RSV (82925XE) AL22 SCB_B7 (82925X) RSV (82925XE) AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 ...
  • Intel 925 | Data Sheet - Page 219
    Ballout and Package Information R Table 12-2. MCH Ballout Sorted By Ball Number Ball # AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 Signal Name SMA_B6 SMA_B3 SMA_B10 VCCSM SWE_B# SCAS_B# SCKE_A0 VCCSM SMA_A11 SMA_A9 SMA_A4 VCCSM SMA_A1 SMA_A10...
  • Intel 925 | Data Sheet - Page 220
    Ballout and Package Information R Figure 12-3. MCH Package Dimensions MCH 220 Intel® 82925X/82925XE MCH Datasheet
  • Intel 925 | Data Sheet - Page 221
    Testability R 13 Testability In the 82925X/82925XE MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it. 13.1 Complimentary Pins Table 13-1 contains pins which ...
  • Intel 925 | Data Sheet - Page 222
    Testability R 13.2 XOR Test Mode Initialization XOR test mode can be entered by pulling reserved ballout RSV (located at F15) and MTYPE low through the de-assertion of external reset (RSTIN#). It is recommended that customers use the following sequence. After power up, hold PWROK, PCIRST#, and ...
  • Intel 925 | Data Sheet - Page 223
    Testability R Table 13-3. XOR Chain #0 Chain 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number M14 K16 G24 K17 M18 K18 F17 M19 K21 K19 H18 J19 F19 G18 K22 M21 J21 H20 H19...
  • Intel 925 | Data Sheet - Page 224
    Testability R Chain 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOR Chain #0 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Ball Number H28 F27 F28 H26 F26 J27 J25 K25 K23 L23 J26 G25 L25 B32 G33 H33 H35 J34 ...
  • Intel 925 | Data Sheet - Page 225
    Testability R Table 13-4. XOR Chain #1 Chain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball Number A28 A27 B27 B25 E24 C26 C27 C28 A31 C31 B31 D29 E28 G29 B34 B33 C32 ...
  • Intel 925 | Data Sheet - Page 226
    Testability R Chain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XOR Chain #1 Output Pin Count 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Ball Number L29 L28 J32 K34 L33 M32 M31 L34 M35 L35 N35 P34 N34 R33 N31 N33 T31 E32 ...
  • Intel 925 | Data Sheet - Page 227
    Testability R Table 13-5. XOR Chain #2 Chain 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Ball Number R32 R34 T35 W35 T33 V34 V33 U33 W33 U34 V30 AA31 AA30 Y30 AB29 V31 V32 R31 R30 AA34 W34 Y35 Y33...
  • Intel 925 | Data Sheet - Page 228
    Testability R Chain 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XOR Chain #2 Output Pin Count 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Ball Number AC35 AB34 AC33 AF34 AH35 AJ34 AG34 AE33 AF33 AG32 AH34 AK34 AG35 AR29 AN32 AN29 AP32 AP30 AJ28 F15 Signal Name SCLK_A2# SCLK_A5# SCLK_A5 ...
  • Intel 925 | Data Sheet - Page 229
    Testability R Table 13-6. XOR Chain #3 Chain 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number W26 U26 V28 V29 W29 W31 AA29 AA28 Y26 W27 AB31 AB27 AE31 AC26 AE27 AE29 ...
  • Intel 925 | Data Sheet - Page 230
    Testability R Chain 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XOR Chain #3 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ball Number AH31 AK33 AJ31 AG28 AJ29 AG31 AH28 AM34 AJ25 AL25 AJ26 AL26 AF23 AG24 C15 Signal Name SDM_B5 SDQ_B45 SDQ_B41 SDQ_B47 SDQ_B44 SDQ_B42 SDQS_B5 SMA_B13 SDQ_B39 ...
  • Intel 925 | Data Sheet - Page 231
    Testability R Table 13-7. XOR Chain #4 Chain 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number U35 U30 AA35 AC34 AG33 AN31 AP31 AK27 AD27 AL30 AJ33 AK31 AF28 AH27 AG27 ...
  • Intel 925 | Data Sheet - Page 232
    Testability R Chain 4 4 4 4 4 4 4 4 4 4 4 4 4 4 XOR Chain #4 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ball Number AR24 AR23 AN23 AH16 AH17 AL17 AF16 AE17 AD17 AN18 AN7 AN3 AL2 AG2 A16 Signal Name SMA_A3 SMA_A6 SMA_A8 SDQS_A3 SDQ_A27 SDQ_A26 SDQ_A25 SDQ_A24 SDQ_A29 SCKE_A2 ...
  • Intel 925 | Data Sheet - Page 233
    Testability R Table 13-8. XOR Chain #5 Chain 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Ball Number Y28 AC30 AD28 AG30 AH30 AF25 AD23 AF24 AG26 AF20 AH19 AD15 AD18 AE20 AK19 AH21 AL18 AF15 AE19 ...
  • Intel 925 | Data Sheet - Page 234
    Testability R Chain 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 XOR Chain #5 Output Pin Count 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ball Number AJ18 AJ21 AN17 AP18 AP17 AR16 AN16 AN14 AN15 AP15 AR15 AP14 AN13 AR9 AG14 AL9 AL5 AH9 B15 Signal Name SCB_B1 (82925X) RSV (82925XE) SDQS_B8# (...
  • Intel 925 | Data Sheet - Page 235
    Testability R Table 13-9. XOR Chain #6 Chain 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number AG17 AF17 AJ17 AK16 AE15 AN19 AP21 AP22 AN22 AR20 AN21 AN20 AP19 AR19 AP7 ...
  • Intel 925 | Data Sheet - Page 236
    Testability R Chain 6 6 6 6 6 6 6 6 6 6 6 6 6 6 XOR Chain #6 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ball Number AJ3 AJ1 AL1 AL3 AG1 AG3 AF2 AH2 AH3 AJ2 AF3 AE3 AE2 AE1 C14 Signal Name SDQ_A13 SDQ_A12 SDM_A1 SDQS_A1 SDQS_A0 SDQ_A6 SDM_A0 SDQ_A7 SDQ_A2 SDQ_A3 SDQ_A1 SDQ_A0 ...
  • Intel 925 | Data Sheet - Page 237
    Testability R Table 13-10. XOR Chain #7 Chain 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number AH25 AG20 AL23 AK21 AP13 AP11 AR12 AR11 AN10 AP10 AN9 AN11 AR8 AP9 AN8 ...
  • Intel 925 | Data Sheet - Page 238
    Testability R Chain 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 XOR Chain #7 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Ball Number AN6 AL6 AK5 AF12 AM5 AH8 AE11 AF11 AG10 AJ7 AJ6 AJ8 AH10 AG11 AH7 K15 Signal Name SDQ_B15 SDQ_B14 SDM_B1 SDQ_B11 SDQS_B1 SDQS_B0 SDQ_B4 SDQ_B5 SDQ_B1 SDQ_B2 ...
  • Intel 925 | Data Sheet - Page 239
    Testability R Table 13-11. XOR Chain #8 Chain 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ball Number F11 C9 H11 A8 E9 C7 E7 A6 B4 C5 E5 D2 G5 F3 H7 G1 J5 H3 K7 J1 L5 K3 R10 L1...
  • Intel 925 | Data Sheet - Page 240
    Testability R Chain 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 XOR Chain #8 Output Pin Count 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Ball Number C10 J11 A9 F9 C8 F7 A7 B3 C6 D5 C2 G6 E3 H8 F1 J6 G3 K8 H1 L6 J3 P10 K1 M8 L3 ...
  • Intel 925 | Data Sheet - Page 241
    Testability R Table 13-12. XOR Chain #9 Chain 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 XOR Chain #9 Output Pin Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ball Number U6 U5 T3 R3 T8 T9 U1 T1 V8 V7 V3 U3 U10 V10 W5 V5 H16 Signal Name DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 ...
  • Intel 925 | Data Sheet - Page 242
    Testability R 13.5 Pads Excluded from XOR Mode(s) A large number of pads do not support XOR testing. The majority of the pads that fall into this category are analog related pins (refer to the Table 13-13). Table 13-13. XOR Pad Exclusion List 3GIO GCLKN GCLKP EXP_COMPO EXP_COMPI FSB HCLKN HCLKP ...



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Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Manual