Intel 925 Data Sheet - Page 10

R Tables Table 2-1. Host Interface Reset and S3 States 31 Table 2-2. System Memory Reset and S3 States 32 Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States 33 Table 2-4. DMI Reset and S3 States 33 Table 2-5. Clocking Reset and S3 States 34 Table 2-6. Miscellaneous Reset and S3 States 34 Table 3-1. Device Number Assignment for Internal MCH Devices 38 Table 4-1. Device 0 Function 0 Register Address Map Summary 45 Table 6-1. Egress Port Register Address Map 93 Table 7-1. DMI Register Address Map Summary 99 Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0 109 Table 9-1. Expansion Area Memory Segments 160 Table 9-2. Extended System BIOS Area Memory Segments 161 Table 9-3. System BIOS Area Memory Segments 161 Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM and 1-MB TSEG 163 Table 9-5. SMM Space Table 168 Table 9-6. SMM Control Table 169 Table 10-1. Sample System Memory Organization with Interleaved Channels 175 Table 10-2. Sample System Memory Organization with Asymmetric Channels 175 Table 10-3. DDR2 DIMM Supported Configurations 178 Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) ...... 179 Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode 180 Table 11-1. Absolute Maximum Ratings 185 Table 11-2. Non-Memory Power Characteristics 186 Table 11-3. DDR2 Power Characteristics 186 Table 11-4. Signal Groups 187 Table 11-5. DC Characteristics 189 Table 12-1. MCH Ballout Sorted By Signal Name 196 Table 12-2. MCH Ballout Sorted By Ball Number 207 Table 13-1. Complimentary Pins to Drive 221 Table 13-2. XOR Chain Outputs 222 Table 13-3. XOR Chain #0 223 Table 13-4. XOR Chain #1 225 Table 13-5. XOR Chain #2 227 Table 13-6. XOR Chain #3 229 Table 13-7. XOR Chain #4 231 Table 13-8. XOR Chain #5 233 Table 13-9. XOR Chain #6 235 Table 13-10. XOR Chain #7 237 Table 13-11. XOR Chain #8 239 Table 13-12. XOR Chain #9 241 Table 13-13. XOR Pad Exclusion List 242 10 Intel® 82925X/82925XE MCH Datasheet