Intel 925 Data Sheet - Page 100

DMIBAR Registers-Direct Media Interface (DMI) RCRB R 7.1 7.1.1 7.1.2 Direct Media Interface (DMI) RCRB Register Details DMIVCECH-DMI Virtual Channel Enhanced Capability Header MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 000h 04010002h RO 32 bits This register indicates DMI Virtual Channel capabilities. Bit 31:20 19:16 15:0 Access & Default Description RO 040h RO 1h RO 0002h Pointer to Next Capability: This field indicates the next item in the list. Capability Version: This field indicates support as a version 1 capability structure. Capability ID: This field indicates this is the Virtual Channel capability item. DMIPVCCAP1-DMI Port VC Capability Register 1 MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 004h 00000001h R/WO, RO 32 bits This register describes the configuration of Virtual Channels associated with this port. Bit 31:12 11:10 9:8 7 6:4 3 2:0 Access & Default Description RO 00b RO 00b RO 000b R/WO 001b Reserved Port Arbitration Table Entry Size (PATS): This field indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). Reference Clock (RC) Fixed at 100 ns. Reserved Low Priority Extended VC Count (LPEVC): This field indicates that there are no additional VCs of low priority with extended capabilities. Reserved Extended VC Count: This field indicates that there is one additional VC (VC1) that exists with extended capabilities. 100 Intel® 82925X/82925XE MCH Datasheet