Intel 925 Data Sheet - Page 120
SSTS1-Secondary Status D1:F0
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Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.14 SSTS1-Secondary Status (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 1Eh 00h RO, R/W/C 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express Graphics side) of the "virtual" PCI-PCI Bridge in the MCH. Bit Access & Default Description 15 R/WC Detected Parity Error (DPE): 0b 1 = The MCH received across the link (upstream) a Posted Write Data Poisoned TLP (EP=1). 14 R/WC Received System Error (RSE): 0b 1 = Secondary side sends an ERR_FATAL or ERR_NONFATAL message due to an error detected by the secondary side, and the SERR Enable bit in the Bridge Control register is 1. 13 R/WC Received Master Abort (RMA): 0b 1 = Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a completion with Unsupported Request Completion Status. 12 R/WC Received Target Abort (RTA): 0b 1 = Secondary Side for Type 1 Configuration Space Header Device (for requests initiated by the Type 1 Header Device itself) receives a completion with Completer Abort Completion Status. 11 RO Signaled Target Abort (STA): Hardwired to 0. The MCH does not generate 0b Target Aborts (the MCH will never complete a request using the Completer Abort Completion status). 10:9 RO DEVSELB Timing (DEVT): Hardwired to 0. 00b 8 R/WC Master Data Parity Error (SMDPE): 0b 1 = The MCH received across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). Note: This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set. 7 RO Fast Back-to-Back (FB2B): Hardwired to 0. 0b 6 Reserved 5 RO 66/60 MHz capability (CAP66): Hardwired to 0. 0b 4:0 Reserved 120 Intel® 82925X/82925XE MCH Datasheet