Intel 925 Data Sheet - Page 16

Introduction R 1.2 1.3 1.3.1 16 Reference Documents Document Title Intel® 925X/925XE Express Chipset Thermal Design Guide Intel® I/O Controller Hub 6 (ICH6) Family Datasheet Advanced Configuration and Power Interface Specification, Version 2.0 Advanced Configuration and Power Interface Specification, Version 1.0b The PCI Local Bus Specification, Version 2.3 PCI Express* Specification, Version 1.0a Document Number/Location http://intel.com/design/chipsets/ designex/301466.htm http://intel.com/design/chipsets/ datashts/301473.htm http://www.acpi.info/ http://www.acpi.info/ http://www.pcisig.com/specificat ions http://www.pcisig.com/specificat ions MCH Overview The MCH connects to the processor as shown in Figure 1-1. A major role of the MCH in a system is to manage the flow of information between its interfaces: the processor interface (FSB), the System Memory interface (DRAM controller), the external graphics interface via PCI Express, and the I/O Controller Hub through the DMI interface. This includes arbitrating between the interfaces when each initiates transactions. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports one or two channels of DDR2 SDRAM. The MCH also supports the new PCI Express based external graphics attach. Thus, the 925X/925XE Express chipset is not compatible with AGP (1X, 2X, 4X, or 8X). To increase system performance, the MCH incorporates several queues and a write cache. The MCH also contains advanced desktop power management logic. Host Interface The MCH is optimized for the Pentium 4 processors in the LGA775 socket. The 82925X MCH supports a FSB frequency of 200 MHz (800 MT/s) using a scalable FSB. The 82925XE MCH supports a FSB frequency of 266 MHz (1066 MT/s). The MCH supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus Protocol. The primary enhancements over the Compatible Mode P6 bus protocol are: Source synchronous double-pumped (2) Address and Source synchronous quad-pumped (4x) Data. The MCH supports 32-bit host addressing, decoding up to 4 GB of the processor's memory address space. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the MCH configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to system memory will be snooped on the host bus. Intel® 82925X/82925XE MCH Datasheet