Intel 925 Data Sheet - Page 107

DMILCTL-DMI Link Control, DMILSTS-DMI Link Status

Get Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU PDF manuals and user guides
UPC - 683728067724
View all Intel 925 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 107 highlights

DMIBAR Registers-Direct Media Interface (DMI) RCRB R 7.1.12 DMILCTL-DMI Link Control MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 088h 0000h R/W 16 bits This register allows control of DMI. Bit Access & Default Description 15:8 Reserved 7 R/W Extended Synch (ES): 0h 1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit from L1 prior to entering L0. 6:2 Reserved 1:0 R/W Active State Link PM Control (APMC): Indicates whether DMI should enter L0s. 00b 00 = Disabled 01 = L0s entry enabled 10 = Reserved 11 = Reserved 7.1.13 DMILSTS-DMI Link Status MMIO Range: Address Offset: Default Value: Access: Size: DMIBAR 08Ah 0001h RO 16 bits This register indicates DMI status. Bit 15:10 9:4 3:0 Access & Default Description Reserved RO Negotiated Link Width (NLW): This field is valid only when the link is in the L0, 00h L0s, or L1 states (after link width negotiation is successfully completed). Negotiated link width is x4 (000100b). All other encodings are reserved. RO Link Speed (LS) 1h Link is 2.5 Gb/s. § Intel® 82925X/82925XE MCH Datasheet 107

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
  • 191
  • 192
  • 193
  • 194
  • 195
  • 196
  • 197
  • 198
  • 199
  • 200
  • 201
  • 202
  • 203
  • 204
  • 205
  • 206
  • 207
  • 208
  • 209
  • 210
  • 211
  • 212
  • 213
  • 214
  • 215
  • 216
  • 217
  • 218
  • 219
  • 220
  • 221
  • 222
  • 223
  • 224
  • 225
  • 226
  • 227
  • 228
  • 229
  • 230
  • 231
  • 232
  • 233
  • 234
  • 235
  • 236
  • 237
  • 238
  • 239
  • 240
  • 241
  • 242
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
Intel
®
82925X/82925XE MCH Datasheet
107
7.1.12
DMILCTL—DMI Link Control
MMIO Range:
DMIBAR
Address Offset:
088h
Default Value:
0000h
Access:
R/W
Size:
16 bits
This register allows control of DMI.
Bit
Access &
Default
Description
15:8
Reserved
7
R/W
0h
Extended Synch (ES):
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.
6:2
Reserved
1:0
R/W
00b
Active State Link PM Control (APMC):
Indicates whether DMI should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
7.1.13
DMILSTS—DMI Link Status
MMIO Range:
DMIBAR
Address Offset:
08Ah
Default Value:
0001h
Access:
RO
Size:
16 bits
This register indicates DMI status.
Bit
Access &
Default
Description
15:10
Reserved
9:4
RO
00h
Negotiated Link Width (NLW):
This field is valid only when the link is in the L0,
L0s, or L1 states (after link width negotiation is successfully completed).
Negotiated link width is x4 (000100b).
All other encodings are reserved.
3:0
RO
1h
Link Speed (LS)
Link is 2.5 Gb/s.
§