Intel 925 Data Sheet - Page 146
PEGLC-PCI Express*-G Legacy Control
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Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.44 PEGLC-PCI Express*-G Legacy Control PCI Device: Address Offset: Default Value: Access: Size: 1 ECh 00000000h RO, R/W 32 bits This register controls functionality that is needed by Legacy (non-PCI Express aware) OS's during run time. Bit Access & Default Description 31:3 RO Reserved 0000 0000h 2 R/W PME GPE Enable (PMEGPE): 0b 0 = Do not generate GPE PME message when PME is received. 1 = Enable. Generate a GPE PME message when PME is received (Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables the MCH to support PMEs on the PCI Express* x16 Graphics Interface port under legacy OSs. 1 R/W Hot-Plug GPE Enable (HPGPE) 0b 0 = Do not generate GPE Hot-Plug message when Hot-Plug event is received. 1 = Enable. Generate a GPE Hot-Plug message when Hot-Plug Event is received (Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the MCH to support Hot-Plug on the PCI Express* x16 Graphics Interface port under legacy OSs. 0 R/W General Message GPE Enable (GENGPE) 0b 0 = Do not forward received GPE assert/deassert messages. 1 = Enable. Forward received GPE assert/deassert messages. These general GPE message can be received via the PCI Express* x16 Graphics Interface port from an external Intel device and will be subsequently forwarded to the Intel® ICH6 (via Assert_GPE and Deassert_GPE messages on DMI). 146 Intel® 82925X/82925XE MCH Datasheet