Intel 925 Data Sheet - Page 169

System Address Map R 9.4.4 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI Express. The SMM software can use this bit to write to video memory while running SMM code out of DRAM. Table 9-6. SMM Control Table G_SMRAME D_LCK 0 x 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 D_CLS X X 0 0 1 1 X 0 1 D_OPEN x 0 0 1 0 1 x x x CPU in SMM Mode x 0 1 x 1 x 0 1 1 SMM Code Access Disable Disable Enable Enable Enable Invalid Disable Enable Enable SMM Data Access Disable Disable Enable Enable Disable Invalid Disable Enable Disable 9.4.5 9.4.6 SMM Space Decode and Transaction Handling Only the processor is allowed to access SMM space. PCI Express and DMI originated transactions are not allowed to SMM space. Processor WB Transaction to an Enabled SMM Address Space Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written to the associated SMM DRAM, even though the space is not open and the transaction is not performed in SMM mode. This ensures SMM space cache coherency when cacheable extended SMM space is used. Intel® 82925X/82925XE MCH Datasheet 169